Multilayer Circuit Interconnection via Programmable Crossbar and Via Addressing
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Solution Overview
Problem
The semiconductor industry faces challenges in further reducing the size of integrated circuit elements, leading to difficulties in increasing performance and planar density, which can be addressed by developing three-dimensional circuits with multiple layers of interconnected circuitry.
Innovation Solution
The Grove Architecture and Thicket Architecture provide new addressing and wiring schemes for multi-layer memristive crossbar memory, allowing for parameterized solutions with varying numbers of memory-plane layers, crossbar width, and via-redundancy factors, ensuring unique addressing and efficient interconnection of programmable crosspoint devices, while the Thicket Architecture eliminates interlayer wiring by using the same wires for nanowires and via-translation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional circuits with multiple layers are created, then planar density and performance are improved, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar circuits to three-dimensional stacked circuits by adding vertical layers. Multiple crossbar arrays are stacked in the vertical dimension, allowing increased planar density without requiring further lateral scaling. This dimensional transition enables higher capacity while maintaining manufacturability through standardized stacking processes.
Solution Approach 2:
The circuit is divided into multiple independent crossbar array layers, each functioning as a separate storage plane. These segmented layers are stacked vertically and interconnected through via structures. The segmentation allows each layer to be independently addressed and managed, reducing the complexity of controlling a monolithic three-dimensional structure while achieving high density through cumulative layer capacity.
2Productivity
If multiple layers of interconnected circuitry are implemented, then performance is improved, but manufacturing complexity increases
Solution Approach 1:
Multiple crossbar array layers are nested vertically in a stacked configuration, with each layer containing crossbar structures and memory elements. The nesting approach allows systematic fabrication where each layer can be processed and integrated in a repeating pattern, reducing manufacturing complexity compared to creating all interconnections in a single complex step. The nested structure enables modular fabrication and assembly.
Solution Approach 2:
Via structures serve as intermediary elements that connect corresponding conductors across different layers. These via intermediaries simplify manufacturing by providing standardized connection points between layers, allowing vertical interlayer routing without requiring complex three-dimensional routing schemes. The via mediators enable systematic layer-to-layer integration while maintaining manufacturing feasibility through established via formation processes.
3Device complexity
If via arrays are reduced, then device complexity is reduced, but addressing capability may be compromised
Solution Approach 1:
Conductors are extended beyond the immediate crossbar array boundaries to reach via structures positioned at peripheral locations. This preliminary extension of conductors allows addressing signals to be routed to vias that connect to other layers, enabling reduced via arrays within each layer while maintaining full addressing capability through interlayer routing. The preliminary conductor extension prepares the signal paths for efficient vertical traversal.
Solution Approach 2:
The same via structures and conductor patterns are replicated across multiple layers in the stack. Instead of designing unique via arrays for each layer, the patent uses identical or similar via configurations repeated throughout the stack. This copying approach reduces design complexity and manufacturing variations while maintaining consistent addressing capability across all layers, as each layer uses the same addressing scheme through its replicated via structures.
Data Source
AI summary
An interconnection architecture for multilayer circuits includes an array of vias and a CMOS layer configured to selectively access the array of vias according to an address. The interconnection architecture also includes a crossbar stack which includes layers of intersecting wire segments with programmable crosspoint devices interposed between intersecting wire segments. The vias are connected to the wire segments such that each programmable crosspoint device is uniquely addressed and every address within a contiguous address space accesses a programmable crosspoint device.