Multi-layer CMOS Quadrature Phase Generator for 5G RF Frontends
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Solution Overview
Problem
Traditional quadrature phase generation circuits, such as those using Lange couplers, are too large for consumer electronic devices, making them unsuitable for miniature RF circuit designs, particularly in the 24 to 43.5 GHz frequency band relevant for 5G development.
Innovation Solution
A miniature on-chip quadrature phase generator using a multi-layer CMOS process with transformers having primary and secondary windings on different substrate layers, achieving a high coupling coefficient and flat phase response, is employed to generate quadrature signals for RF transceivers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional quarter wavelength coupled transmission line (Lange coupler) is used to generate quadrature signals, then low insertion loss and good return loss are achieved, but chip size becomes large which is not suitable for consumer electronic device design
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional multi-layer structure. By stacking transformer windings across multiple substrate layers, the design achieves high coupling coefficients without requiring large lateral chip area, thus resolving the contradiction between performance and size.
Solution Approach 2:
The patent implements nested winding structures where primary and secondary windings are interlaced across multiple layers. This nesting approach maximizes magnetic coupling within a compact volume, enabling high coupling coefficients while minimizing the occupied chip area.
2Area of stationary object
If multi-layer CMOS process with transformers on different substrate layers is used, then high coupling coefficient and flat phase response are achieved in compact size, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes the multi-layer CMOS process for multiple purposes: signal transmission, magnetic coupling, and phase transformation. The same structural layers that provide electrical connectivity also provide magnetic coupling and phase quadrature, reducing the need for additional dedicated components and processes.
3Adaptability or versatility
If wide frequency band (24 to 43.5 GHz) coverage is achieved, then adaptability for 5G development is improved, but maintaining flat phase response and low insertion loss across the band becomes more difficult
Solution Approach 1:
The patent optimizes key parameters including winding geometry, layer spacing, and transformer configuration to achieve wideband performance. By carefully controlling these parameters, the design maintains flat phase response and low insertion loss across the 24 to 43.5 GHz frequency range, enabling broad 5G band compatibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient quadrature signal generation with low insertion loss and good return loss across a wide frequency band, suitable for compact RF frontend integrated circuits in consumer devices.
Implementation Method 1
A high coupling coefficient, which can enhances wide band performance and flat quadrature phase difference response, is obtained from small thickness between layers
Data Source
AI summary
An RF frontend circuit includes an RF transceiver and a frequency synthesizer to perform frequency synthetization in a wide frequency spectrum. The frequency synthesizer generates an LO signal to the RF transceiver. The frequency synthesizer includes a quadrature signal generator to generate a quadrature LO signal based on the LO signal. The quadrature signal generator includes a first transformer. A first primary winding of the first transformer is disposed on a first substrate layer of the IC and a secondary winding of the first transformer is disposed on a second substrate layer of an IC. A second transformer is coupled to the first transformer in series. A second primary winding of the second transformer is disposed on the first substrate layer of the IC and a secondary winding of the second transformer is disposed on the second substrate layer of the IC.