Multilayer Upper Conductive Structure to Limit Etch Re-Deposition
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Solution Overview
Problem
The challenge in semiconductor chip fabrication is the re-deposition of conductive material onto sidewalls and upper surfaces during plasma etching, which affects etching rates and increases costs due to the need for waferless auto-clean processes, leading to yield loss and RC delay in integrated chips.
Innovation Solution
A multilayer stack comprising a first conductive layer, a dielectric layer, and a second conductive layer is formed, where the dielectric layer prevents plasma from reaching the first conductive layer, thereby reducing re-deposition and facilitating accurate removal of metal oxides, ensuring good electrical connections and maintaining etching rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If plasma etching is used to remove metal oxides, then cleaning effectiveness is improved, but re-deposition of conductive material occurs on sidewalls and upper surfaces
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the plasma etching process and the first conductive layer. This dielectric layer acts as a protective barrier that prevents conductive material from being re-deposited onto the first conductive layer during plasma etching, while still allowing the plasma to effectively remove metal oxides from exposed surfaces.
Solution Approach 2:
The dielectric layer is formed in advance before the plasma etching process. This preliminary action prepares the structure by creating a protective barrier that will prevent re-deposition during the subsequent cleaning step, eliminating the need for additional clean steps afterward.
2Manufacturing precision
If waferless auto-clean processes are performed to remove re-deposited material, then cleanliness is improved, but fabrication time and costs increase
Solution Approach 1:
The dielectric layer is formed in advance to prevent re-deposition during plasma etching. By taking this preventive action beforehand, the need for subsequent waferless auto-clean processes is eliminated, thereby reducing fabrication time and increasing productivity while maintaining cleanliness.
Solution Approach 2:
The harmful re-deposition effect is extracted or prevented by introducing the dielectric layer as a separate protective component. This isolation prevents the conductive material from being re-deposited in the first place, eliminating the need for additional cleaning operations.
3Productivity
If feature sizes are decreased to increase production efficiency, then productivity is improved, but fabrication difficulty increases
Solution Approach 1:
The dielectric layer serves as an intermediary protective layer that simplifies the fabrication process for small features. By preventing re-deposition, it ensures cleaner interfaces and better electrical connections, which is particularly important when working with smaller, more densely packed features where contamination has a greater impact.
Solution Approach 2:
The plasma etching process, which normally causes harmful re-deposition, is converted into a beneficial process by adding the dielectric layer. The plasma can now perform its cleaning function effectively without the negative side effect of re-deposition, enabling better control over metal oxide removal in scaled-down devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of waferless auto-clean processes, decreases fabrication time and costs, and minimizes yield loss by preventing re-deposition of conductive material, thus enhancing the performance and efficiency of integrated chip production.
Implementation Method 1
A method for forming an upper conductive structure includes forming a first conductive layer over a passivation structure that is along a topmost conductive wire of an interconnect structure. A dielectric layer is formed over the first conductive layer. A patterning process is performed on the dielectric layer, the first conductive layer, and the passivation structure to form an opening over the topmost conductive wire. A cleaning process is performed on the dielectric layer and the topmost conductive wire to remove a metal oxide. A second conductive layer is formed over the dielectric layer and the topmost conductive wire, wherein the second conductive layer lines the opening.
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes an interconnect structure overlying a semiconductor substrate and comprising a conductive wire. A passivation structure overlies the interconnect structure. An upper conductive structure overlies the passivation structure and comprises a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along a top surface of the dielectric layer and penetrates through the first conductive layer and the passivation structure to the conductive wire.