Multilayer Semiconductor Connection-Line Testing for Failure Localization
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Solution Overview
Problem
Conventional semiconductor device testing methods face challenges in efficiently locating and analyzing failures in multi-layered substrates due to increased complexity with more connections, leading to longer diagnosis times.
Innovation Solution
A semiconductor device and testing method that includes a connection member forming a connection line across multiple substrates with a power supply terminal and observation terminal, allowing for observation and measurement of current-carrying states to detect resistance anomalies indicative of failure locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple substrates are connected by more connections to achieve multi-functioning and higher integration, then the functionality and integration level are improved, but the difficulty of locating failure and analysis time increase
Solution Approach 1:
The patent divides the multi-layer substrate into multiple independent layers, each with its own test terminals. This segmentation allows individual layer testing without affecting other layers, reducing the complexity of failure location in highly integrated multi-functional devices.
Solution Approach 2:
The patent introduces test terminals as intermediary elements that provide access to internal connection points. These test terminals act as mediators between external testing equipment and internal connections, enabling failure detection without disrupting the complex multi-functional integration.
2Adaptability or versatility
If multiple substrates are connected by more connections to achieve multi-functioning and higher integration, then the functionality and integration level are improved, but the analysis time increases
Solution Approach 1:
By segmenting the substrate into independent testable layers with separate test terminals, the patent enables parallel or sequential testing of individual layers. This reduces the time required to analyze failures in highly integrated multi-functional devices compared to testing the entire integrated structure as a single unit.
Solution Approach 2:
The patent incorporates test terminals during the manufacturing process, performing preliminary setup for future failure analysis. This preliminary action of embedding test access points during fabrication significantly reduces the time required for subsequent failure analysis in multi-functional integrated devices.
3Ease of manufacture
If conventional testing methods are used on multi-layer substrates, then the existing testing infrastructure can be maintained, but the ability to detect and locate failures deteriorates
Solution Approach 1:
The test terminals serve as intermediary access points that bridge conventional testing infrastructure with multi-layer substrate internal connections. These intermediaries enable existing testing equipment to effectively detect and locate failures in complex multi-layer structures without requiring new testing hardware.
Solution Approach 2:
The patent replaces complex mechanical disassembly methods with electrical testing through test terminals. Instead of physically separating layers to test connections, the system uses electrical measurements through accessible test terminals, making failure detection easier while maintaining manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Facilitates rapid detection of failure locations by observing current-carrying states across multiple substrates, reducing diagnosis time and improving analysis efficiency.
Implementation Method 1
a connection member that is electrically connected on joint surfaces of the plurality of semiconductor substrates to form at least one connection line that extends over the plurality of semiconductor substrates
Implementation Method 2
an observation terminal connected to another end of the connection line... observing current-carrying states to detect resistance anomalies indicative of failure locations
Data Source
AI summary
An abnormality resulting from connection between a plurality of substrates is easily detected in a semiconductor device including a multilayer semiconductor substrate. The semiconductor device includes a plurality of semiconductor substrates, a connection member, a power supply terminal, and an observation terminal. The connection member is electrically connected on joint surfaces of the plurality of semiconductor substrates to form at least one connection line that extends over the plurality of semiconductor substrates. The power supply terminal is connected to one end of the connection line, and the observation terminal is connected to the other end of the connection line. Power is supplied to the power supply terminal. The observation terminal is used to observe a resistance state of the connection line.