Multi-Layer Copper Pillar for Thermal Stress Mitigation
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Solution Overview
Problem
Copper pillar technology in chip-to-substrate connections fails to effectively mitigate thermal coefficient mismatch between the chip and substrate, leading to stress-related fractures and delaminations due to copper's high Young's modulus and thermal expansion, which are not adequately addressed by existing lead-free solutions.
Innovation Solution
A multi-layer copper pillar structure is introduced, featuring intermediate layers with lower modulus of elasticity than copper, which absorb stress during the cooling cycle and allow the pillar to tilt or slide, compensating for thermal expansion mismatch, thereby reducing stress on the chip and substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper pillar technology is used to replace leaded solder interconnects, then electrical conductivity and connection density are improved, but stress mitigation capability deteriorates due to copper's high Young's modulus and thermal expansion
Solution Approach 1:
The patent applies composite materials by creating a multi-layer pillar structure consisting of copper layers combined with intermediate layers of materials having lower modulus of elasticity (such as solder or other ductile metals). This composite structure integrates the high electrical conductivity of copper with the stress-absorbing capabilities of the intermediate layers, thereby resolving the contradiction between electrical performance and stress mitigation.
Solution Approach 2:
The patent implements local quality by introducing intermediate layers with specific material properties at strategic positions within the pillar structure. These intermediate layers are placed specifically at interfaces where stress concentration occurs, providing localized stress absorption and deformation capability while maintaining the overall copper pillar's electrical conductivity and structural integrity.
2Reliability
If copper pillar technology is used to replace leaded solder interconnects, then connection density is improved, but thermal coefficient mismatch between chip and substrate worsens
Solution Approach 1:
The multi-layer composite structure enables thermal coefficient matching by combining copper (high thermal expansion) with intermediate layers (lower thermal expansion). This composite approach creates an effective thermal expansion coefficient that better matches the chip-substrate system, resolving the adaptability issue while maintaining high connection density.
Solution Approach 2:
The patent changes the physical parameters of the interconnect structure by introducing intermediate layers with different thermal and mechanical properties. This modifies the overall thermal expansion behavior of the pillar, enabling better adaptation to thermal coefficient mismatch between chip and substrate while preserving the high connection density advantage of copper pillars.
3Ease of manufacture
If copper pillar technology is used to replace leaded solder interconnects, then manufacturing capability is improved, but stress-induced damage increases during cooling cycle
Solution Approach 1:
The patent applies beforehand cushioning by incorporating intermediate layers that are specifically designed to absorb and cushion thermal stresses before they can propagate to the chip or substrate. These intermediate layers act as pre-positioned stress buffers that mitigate harmful stresses during the cooling cycle, preventing fractures and delaminations while maintaining manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-layer copper pillar design effectively absorbs stresses, preventing chip damage and increasing module yield by incorporating low strength, high ductility metal layers that can deform to accommodate thermal excursions, thus enhancing the reliability of chip-to-substrate connections.
Implementation Method 1
The intermediate layer has a lower modulus of elasticity than that of the two copper layers and thereby is configured to absorb stress imposed during a cooling cycle of an interconnect process
Implementation Method 2
copper has a high Young's modulus and a high thermal expansion. This being the case, copper is not an ideal candidate for mitigating thermal coefficient (TCE) mismatch between the chip and the substrate
Implementation Method 3
a modulated copper pillar having at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions
Data Source
AI summary
A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.