Multilayer Substrate Die-to-Die Links for Die Offset Tolerance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices require separate and external die-to-die links that occupy valuable substrate space and do not account for die-to-die variations, necessitating a more robust and scalable integration solution.
Innovation Solution
Integrate die-to-die links within the packaging substrate, forming them only where needed, using a substrate with alternating conducting and dielectric layers to accommodate die-to-die offset and spacing variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If die-to-die links are implemented using external interposers or interconnect bridges, then connectivity between dies is achieved, but valuable substrate space is occupied and manufacturing complexity increases
Solution Approach 1:
The patent merges the die-to-die link functionality with the packaging substrate by integrating conductive traces and vias directly into the substrate layers. This eliminates the need for separate external interposers or interconnect bridges, thereby reducing substrate space occupation while maintaining connectivity functionality.
Solution Approach 2:
The patent utilizes multiple layers within the substrate (including conductive layers, dielectric layers, and via structures) to create three-dimensional interconnect paths. This layered approach allows die-to-die links to be formed within the substrate volume rather than requiring external planar connections, reducing the footprint on the substrate surface.
2Reliability
If external die-to-die links are used, then die connectivity is established, but the solution does not account for die-to-die offset and spacing variations
Solution Approach 1:
The patent pre-forms conductive traces and via structures within the substrate during substrate manufacturing, before die attachment. These pre-formed interconnect structures are designed with tolerance compensation features that automatically accommodate die-to-die offset and spacing variations, ensuring reliable connections without requiring precise die placement.
Solution Approach 2:
The patent employs conductive traces and via structures with designed geometric parameters (such as trace width, via diameter, and layer thickness) that provide tolerance compensation. These parameter variations in the interconnect structures allow the system to adapt to die placement variations while maintaining electrical connectivity.
Data Source
Figure 1
Figure 2
Figure 3A
AI summary
Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package or a chip package including two or more high-density layers for die-to-die interconnections. In various embodiments, a semiconductor device (100) includes a substrate comprising two or more first layers (200) and a second layer (112). A first length (L1) of the two or more first layers (200) can be less than a second length (L2) of the second layer (112). The semiconductor device (100) can further include a first die (104a) coupled to the second layer (112) of the substrate and a second die (104b) coupled to the second layer (112). At least one of the two or more first layers (200) comprises a connector (202) coupling the first die (104a) to the second die (104b).