Multilayer Display Data Link Lines for Parasitic Capacitance Equalization

The patent introduces dummy data link lines as intermediary elements between the functional data link lines. These dummy lines act as mediators that absorb or balance the parasitic capacitance effects, preventing the harmful capacitance from causing vertical line defects in the display. The dummy lines are strategically positioned to equalize the total parasitic capacitance experienced by each data link line.

The patent modifies the electrical parameters of the data link line system by adding dummy lines with specific capacitance characteristics. This changes the overall parasitic capacitance parameter of each data link line to be equal, thereby eliminating the parameter imbalance that causes display defects. The dummy lines are designed with specific physical dimensions and materials to achieve the desired capacitance value.

Dummy data link lines serve as intermediary compensating elements that balance the parasitic capacitance across all data link lines. By introducing these additional lines, the system achieves equal total capacitance for each data link line, ensuring consistent data voltage output to all pixels connected through different data link lines.

The patent creates equipotential conditions for all data link lines by ensuring they have equal total parasitic capacitance. This is achieved by adding dummy lines with specific capacitance values to balance the inherent capacitance differences among the original data link lines, thereby ensuring that all data link lines operate under equivalent electrical conditions and deliver consistent voltage levels.