Multilayer Display Pixel Circuit Layout for Higher Resolution
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Solution Overview
Problem
There is a demand for compact and high-resolution display devices with improved space arrangement, connection structures, and enhanced image quality, particularly in thin film transistors, capacitors, and lines.
Innovation Solution
A display device design incorporating a light emitting element, transistors, and capacitors with specific semiconductor layers and overlapping channels, utilizing a unique transistor and capacitor arrangement to enhance resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If transistors and capacitors are arranged in a conventional single-layer configuration, then the device structure is simple, but the resolution and space utilization are insufficient
Solution Approach 1:
The patent transitions from a conventional planar single-layer arrangement to a three-dimensional multi-layer configuration. The first semiconductor layer contains the first and third transistors, while the second semiconductor layer contains the second and fourth transistors, along with capacitors distributed across both layers. This vertical stacking approach increases spatial utilization and enables higher resolution displays by packing more functional elements into a compact area.
Solution Approach 2:
The patent implements a nested structure where the second semiconductor layer is positioned above the first semiconductor layer, with capacitors and transistor channels interlaced across the layers. The first capacitor's first electrode is connected to the gate electrode of the first transistor, while its second electrode connects to the second transistor, creating an integrated nested architecture that optimizes space and improves resolution.
2Manufacturing precision
If more transistors and capacitors are integrated to improve resolution, then image quality enhances, but the device structure becomes more complex
Solution Approach 1:
The patent assigns multiple functions to different transistor configurations within the multi-layer structure. The first transistor applies driving current to the light emitting element, the second transistor applies data voltage to the capacitor, the third transistor diode-connects the first transistor for compensation, and the fourth transistor applies initialization voltage. This multi-functional arrangement within a unified two-layer architecture improves image quality while managing structural complexity through functional integration.
3Volume of moving object
If a multi-layer semiconductor structure is used to improve space arrangement, then compactness increases, but manufacturing difficulty increases
Solution Approach 1:
The patent divides the semiconductor structure into two distinct layers: the first semiconductor layer containing the first and third transistors, and the second semiconductor layer containing the second and fourth transistors. This segmentation allows for modular fabrication processes, where each layer can be manufactured and tested separately before integration, thereby reducing overall manufacturing difficulty despite the increased compactness achieved through vertical stacking.
Data Source
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AI summary
A display device includes a light emitting element (LE), a first transistor (T1) which applies a driving current to the light emitting element, a first capacitor (C1) including a first electrode connected to a gate electrode of the first transistor and a second electrode, a second transistor which applies a data voltage to the second electrode of the first capacitor in response to a write gate signal, a third transistor (T3) which diode-connects the first transistor in response to a compensation gate signal, and a fourth transistor (T4) which applies an initialization voltage to an anode of the light emitting element in response to an initialization gate signal. A channel (CH1) of the first transistor and a channel (CH3) of the third transistor are in a first semiconductor layer. A channel of the second transistor and a channel of the fourth transistor are in a second semiconductor layer arranged on the first semiconductor layer.