Multi-Layer Emitter Metallization for Closer Row Spacing
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Solution Overview
Problem
Time-of-flight systems face limitations in reducing the spacing between rows of emitters due to fabrication constraints, which affects the angular and vertical resolution, and reducing metallization layer width increases resistance, reducing system efficiency.
Innovation Solution
A method involving a first metallization layer for a first set of emitters and a second metallization layer for a second set of emitters, where the second metallization layer at least partially overlaps the first, with a dielectric layer insulating them, allowing for reduced spacing between rows and increased metallization layer width to improve efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the spacing between rows of emitters is reduced to improve vertical resolution, then manufacturing precision and device complexity increase due to fabrication constraints
Solution Approach 1:
The patent transitions from a single-plane metallization layout to a multi-layer three-dimensional structure. By stacking metallization layers vertically and using vias to connect them, the design accommodates reduced emitter spacing while maintaining manufacturable trace widths. This dimensional change allows the system to achieve finer vertical resolution without hitting the fabrication precision limits of single-layer designs.
2Measurement precision
If the metallization layer width is reduced to accommodate smaller emitter spacing, then electrical resistance increases and system efficiency decreases
Solution Approach 1:
Instead of reducing metallization width in the horizontal plane to accommodate smaller emitter spacing, the patent adds vertical dimensionality with multiple metallization layers. This allows each layer to maintain adequate trace widths for low resistance, while the stacked configuration enables closer emitter spacing. The via connections between layers complete the electrical pathways without compromising conductor cross-sectional area.
Solution Approach 2:
The patent combines multiple metallization layers into a unified electrical network. By merging the conductive paths across layers through via connections, the design achieves both close emitter spacing and sufficient current-carrying capacity. The combined multi-layer structure effectively increases the total conductive cross-section, maintaining low resistance despite reduced horizontal dimensions.
Data Source
AI summary
A method for fabricating an array of emitters may include providing a first metallization layer for a first set of emitters of a first channel, wherein the first metallization layer comprises a first interchannel portion positioned between the first set of emitters and a second set of emitters of a second channel. The method may include depositing a dielectric layer on the first interchannel portion of the first metallization layer. The method may include providing a second metallization layer for the second set of emitters, wherein the second metallization layer comprises a second interchannel portion positioned between the first set of emitters and the second set of emitters, and wherein the second interchannel portion of the second metallization layer at least partially overlaps the first interchannel portion of the first metallization layer.