Multi-Layer Encapsulation Stack for Humidity-Resistant Semiconductors
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Solution Overview
Problem
Semiconductor devices, particularly those using wide bandgap materials like SiC and Group III nitrides, face challenges with environmental protection due to defects in PECVD SiN layers, which allow moisture to penetrate and cause degradation, especially in high temperature and high humidity environments.
Innovation Solution
A multi-layer encapsulation stack comprising a conformal first encapsulation layer and a self-planarizing second encapsulation layer, where the second layer is cured to provide a hardened, planar surface, using materials with a cure temperature within the thermal budget of the semiconductor device to ensure complete curing without damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PECVD SiN layer is used as environmental barrier, then device protection is provided, but defects such as pin holes and columnar structures allow moisture penetration
Solution Approach 1:
The encapsulation structure is divided into multiple layers: a first encapsulation layer (SiN) providing environmental barrier, and a second encapsulation layer (self-planarizing material) filling defects and providing planar protection. This segmentation allows each layer to address specific protection needs while compensating for the limitations of individual layers.
Solution Approach 2:
The patent combines different encapsulation materials (SiN and self-planarizing material) into a composite encapsulation structure. The SiN layer provides chemical stability and environmental barrier, while the self-planarizing layer provides defect filling and planar protection, creating a composite system that overcomes the weaknesses of single materials.
2Manufacturing precision
If self-planarizing encapsulation layer is added, then planar surface and moisture barrier are improved, but device complexity increases
Solution Approach 1:
The second encapsulation layer is formulated as a self-planarizing material that automatically flows and levels to create a planar surface without requiring additional planarization processing steps. This self-service property simplifies the overall manufacturing process despite adding an encapsulation layer.
Solution Approach 2:
The patent controls the thickness ratio between the first and second encapsulation layers (T1/T2 between 0.20-0.29) to optimize both protection performance and process simplicity. This parameter control ensures adequate protection while maintaining manageable device complexity.
3Reliability
If curing temperature is increased to ensure complete curing, then encapsulation layer performance is improved, but semiconductor device may be damaged
Solution Approach 1:
The patent selects a self-planarizing encapsulation material with a cure temperature (≤275°C) that is lower than the maximum temperature the semiconductor device can withstand. This parameter selection enables complete curing of the encapsulation layer while preventing damage to the underlying semiconductor structure.
Solution Approach 2:
The encapsulation layer is cured at a controlled temperature before subsequent high-temperature processing steps. This preliminary curing action ensures the encapsulation layer is fully formed and protective before the device undergoes higher temperature processing, preventing damage during later steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-layer encapsulation stack enhances environmental protection by preventing moisture ingress and maintaining device performance, with improved humidity resistance and reliability, as demonstrated by reduced bowing and increased reliability during stress testing.
Implementation Method 1
a self-planarizing encapsulation layer on the non-planar encapsulation layer and comprising a planarized surface that is opposite the non-planar encapsulant surface
Implementation Method 2
a non-planar encapsulation layer on the non-planar surface of the metallization layer
Data Source
AI summary
A transistor device includes a substrate, a semiconductor structure on the substrate, a metallization layer comprising a non-planar surface on a surface of the semiconductor structure, a non-planar encapsulation layer on the non-planar surface of the metallization layer, the non-planar encapsulation layer comprising a non-planar encapsulant surface that is opposite the non-planar surface, and a self-planarizing encapsulation layer on the non-planar encapsulation layer and comprising a planarized surface that is opposite the non-planar encapsulant surface.


