Multi-Layer Etch Stop Stack for BEOL Contact Adhesion
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Solution Overview
Problem
Existing etch stop layers in back-end-of-line (BEOL) interconnect structures face challenges in maintaining sufficient process windows when applied to device structures with fine-pitch metal, thick metal structures, radio frequency (RF) devices, and high-performance computing (HPC) devices, as they do not adequately address the increased complexity and tighter power, performance, and area (PPA) requirements in semiconductor manufacturing.
Innovation Solution
The implementation of multi-layer etch stop layer (ESL) structures, including a lower ESL of metal nitride or nitrogen-doped silicon carbide, an optional middle ESL of oxygen-doped silicon carbide, and an upper ESL of metal oxide, which are deposited over copper or tungsten conductive features to enhance adhesion and etch resistance, along with plasma treatment to create a nitrogen-rich surface for improved copper adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If single-layer etch stop layers are used in BEOL interconnect structures, then the manufacturing process is simpler, but they fail to provide sufficient adhesion and etch resistance for fine-pitch metal and thick metal structures
Solution Approach 1:
The patent divides the single etch stop layer into multiple segmented layers (first ESL and second ESL) with different material compositions and functions. The first ESL (e.g., silicon nitride) provides etch resistance, while the second ESL (e.g., silicon oxide) provides adhesion to copper features, allowing each layer to be optimized for its specific function rather than requiring a single layer to perform both roles
Solution Approach 2:
The patent employs composite material structures where the etch stop layer system consists of multiple materials with complementary properties. The combination of silicon nitride (high etch resistance) and silicon oxide (good adhesion) creates a composite structure that achieves both adhesion and etch resistance requirements that neither material could satisfy alone
2Productivity
If device dimensions are scaled down to improve production efficiency and lower costs, then manufacturing productivity increases, but process complexity and tighter PPA windows increase
Solution Approach 1:
By segmenting the etch stop layer into multiple specialized layers, the patent enables precise control over etch processes for scaled devices. Each layer can be tailored to specific etch conditions required by fine-pitch features, allowing continued scaling while maintaining process control and avoiding the need for complete process redesign
Solution Approach 2:
The patent changes material parameters and layer thicknesses to optimize performance at scaled dimensions. By adjusting the thickness and composition of each ESL layer, the system maintains appropriate adhesion and etch resistance characteristics even as device features become smaller and more densely packed
3Ease of manufacture
If existing etch stop layers are applied to RF and HPC devices, then device fabrication continues, but they do not adequately address tighter power, performance, and area requirements
Solution Approach 1:
The patent applies local quality by making different regions of the etch stop layer system have different properties. The first ESL and second ESL are positioned at different locations and have different material characteristics optimized for their specific functions, allowing the structure to meet stringent PPA requirements through localized material optimization rather than uniform properties throughout
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed ESL structures provide enhanced adhesion and etch resistance, enabling precise etch endpoint detection and reducing parasitic capacitance, thus supporting the fabrication of advanced semiconductor devices with improved power, performance, and area (PPA) characteristics.
Implementation Method 1
treating the workpiece with a nitrogen-containing plasma
Implementation Method 2
depositing a first etch stop layer (ESL) over the workpiece
Data Source
AI summary
Contact structures and methods of forming the same are provided. A method according to the present disclosure includes receiving a workpiece including a conductive feature embedded in a first dielectric layer, treating the workpiece with a nitrogen-containing plasma, after the treating, depositing a first etch stop layer (ESL) over the workpiece, depositing a second ESL over the first ESL, depositing a second dielectric layer over the second ESL, forming an opening through the second dielectric layer, the second ESL and the first ESL to expose the conductive feature, and forming a contact via in the opening. The first ESL includes aluminum nitride or silicon carbonitride and the second ESL includes aluminum oxide or silicon oxycarbide.