Multi-Layer Insulating Film Stack for FinFET RC Delay Reduction
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Solution Overview
Problem
In FinFET devices, the integration density improvements lead to challenges in reducing RC delay and threshold voltage variation due to parasitic capacitance and device leakage, which existing technologies have not adequately addressed.
Innovation Solution
A multi-layered insulating film stack is formed with a non-conformal first dielectric layer lining the sidewalls and bottom of openings between metal gates, followed by a second dielectric layer with a lower dielectric constant to fill the gaps, reducing the overall dielectric constant and balancing parasitic capacitance, and a plasma process is used to treat the bottom portion of the first dielectric layer to reduce fixed charges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-layer dielectric structure is used to fill gaps between metal gates, then the manufacturing process is simple, but the parasitic capacitance cannot be balanced and RC delay is high
Solution Approach 1:
The single-layer dielectric structure is segmented into multiple layers with different dielectric constants. The first dielectric layer (higher k-value) fills the bottom portion of the gap, while the second dielectric layer (lower k-value) fills the upper portion, allowing differential capacitance control to reduce RC delay
Solution Approach 2:
Different regions of the dielectric structure are assigned different material properties. The bottom region uses a higher dielectric constant material to maintain necessary capacitance, while the upper region uses a lower dielectric constant material to reduce parasitic capacitance and overall RC delay
2Reliability
If fixed charges are present in the dielectric layer to balance parasitic capacitance, then the capacitance balancing is achieved, but device leakage increases
Solution Approach 1:
Fixed charges are extracted or removed from the dielectric structure through plasma treatment processes. The plasma process eliminates trapped charges that would otherwise cause leakage currents, while the multi-layer dielectric configuration maintains parasitic capacitance balancing through its geometric and material design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces RC delay, balances parasitic capacitance, and minimizes device leakage by optimizing the dielectric constant and charge distribution within the insulating film stack.
Implementation Method 1
a plasma process is used to treat the bottom portion of the first dielectric layer to reduce fixed charges
Data Source
AI summary
A method for forming a semiconductor device includes: forming a gate structure over a fin, where the fin protrudes above a substrate; forming an opening in the gate structure; forming a first dielectric layer along sidewalls and a bottom of the opening, where the first dielectric layer is non-conformal, where the first dielectric layer has a first thickness proximate to an upper surface of the gate structure distal from the substrate, and has a second thickness proximate to the bottom of the opening, where the first thickness is larger than the second thickness; and forming a second dielectric layer over the first dielectric layer to fill the opening, where the first dielectric layer is formed of a first dielectric material, and the second dielectric layer is formed of a second dielectric material different from the first dielectric material.