Multilayer Filter Capacitor Layout for Low Capacitance and Inductance
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Solution Overview
Problem
Existing multilayer filters face challenges in achieving low capacitance values and minimizing parasitic inductance, especially at high frequencies, due to the need for smaller capacitive areas and the negative impact of parasitic inductance on performance.
Innovation Solution
A multilayer filter design featuring a capacitor with a small capacitive area formed by overlapping conductive layers, where vias are arranged to minimize inductance and prevent voltage differences across the conductive layers, allowing for a reduced capacitive area and low inductance, and the use of dielectric materials with low dielectric constants to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the capacitive area is reduced to achieve low capacitance values, then the capacitance decreases which is useful for high frequency filtering, but the parasitic inductance increases which negatively affects performance
Solution Approach 1:
The patent transitions from planar via arrangement to a three-dimensional stacked configuration. Multiple vias are arranged in vertical stacks through different conductive layers, allowing the capacitive area to be minimized while the via inductance is reduced through the compact vertical integration. This dimensional change enables simultaneous achievement of low capacitance and low inductance by exploiting the Z-direction stacking.
Solution Approach 2:
The patent implements nested via structures where multiple vias are positioned in overlapping vertical projections, creating a nested configuration. The first and second vias are stacked such that their horizontal projections overlap or are adjacent, forming a compact nested arrangement that minimizes the overall capacitive footprint while reducing parasitic inductance through the nested via pathway.
2Quantity of substance
If the capacitive area is reduced to achieve low capacitance values, then high frequency filtering capability is improved, but the manufacturing precision requirements increase due to alignment sensitivity
Solution Approach 1:
By moving the via arrangement into the vertical dimension with stacked configurations, the patent reduces sensitivity to horizontal alignment errors. The overlapping vertical projections of nested vias provide a tolerance buffer, allowing greater manufacturing flexibility while maintaining the low capacitive area required for high frequency operation.
Solution Approach 2:
The nested via arrangement where vias overlap in their horizontal projections creates a self-aligning effect. The nested configuration ensures that even with manufacturing variations, the vias maintain their electrical connection pathway, reducing the impact of alignment errors on the overall capacitor performance.
3Reliability
If vias are placed within the overlapping area to connect conductive layers, then electrical connection is achieved, but parasitic inductance increases and capacitance value increases
Solution Approach 1:
The patent places vias in nested configurations where their horizontal projections overlap or are adjacent rather than separated. This nested via arrangement creates compact electrical connection pathways that minimize loop area and reduce parasitic inductance while maintaining reliable electrical connection between conductive layers.
Solution Approach 2:
The via connections are arranged in the vertical dimension with stacked configurations, allowing the capacitive area in the horizontal plane to be minimized. The vertical stacking of vias provides efficient electrical connection while reducing the horizontal footprint and associated parasitic inductance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves low inductance and capacitance, ensuring excellent performance characteristics such as low insertion loss and steep roll-off, while being insensitive to misalignment and maintaining performance across a wide range of temperatures.
Implementation Method 1
a first conductive layer overlaps the second conductive layer in each of the first direction and second direction at an overlapping area to form a capacitor
Implementation Method 2
the use of dielectric materials with low dielectric constants to enhance performance
Data Source
AI summary
A multilayer filter may include a plurality of dielectric layers stacked in a Z-direction. A first conductive layer may overlie one of the dielectric layers, and a second conductive layer may overlie another of the dielectric layers and be spaced apart from the first conductive layer in the Z-direction. A first via may be connected with the second conductive layer at a first location. A second via may be connected with the second conductive layer at a second location that is spaced apart in a first direction from the first location. The first conductive layer may overlap the second conductive layer at an overlapping area to form a capacitor. At least a portion of the overlapping area may be located between the first location and the second location in the first direction. The second conductive layer may be free of via connections that intersect the overlapping area.