Multilayer Floating Gate for Flash Memory Voltage Distribution
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Solution Overview
Problem
Conventional flash memory devices face challenges with increased threshold voltage distribution and cross-talk as they miniaturize, leading to reduced production yield and durability issues due to the inability to precisely control the size of the floating gate and increased mechanical stresses.
Innovation Solution
A multilayer floating gate structure is introduced, comprising a first thin storage electrode, a second thick storage electrode, and a third thin storage electrode, with a source/drain provided below the opposite sidewalls, to reduce threshold voltage distribution and mechanical stresses while maintaining a suitable coupling ratio, thereby improving durability and reducing cross-talk between cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the floating gate thickness is reduced according to miniaturization of cell elements, then the size of memory devices is reduced, but the coupling ratio between control electrode and floating electrode is reduced
Solution Approach 1:
The patent transitions from a single-layer floating gate to a multilayer floating gate structure, adding vertical dimensionality. This allows the floating gate to maintain adequate thickness for coupling ratio while reducing lateral dimensions for miniaturization. The multilayer structure distributes the thickness requirement across multiple layers, resolving the contradiction between size reduction and coupling ratio maintenance.
Solution Approach 2:
The floating gate is segmented into multiple thin layers instead of a single thick layer. This segmentation allows each layer to be sufficiently thin for miniaturization while the cumulative thickness maintains the required coupling ratio. The segmented structure also reduces mechanical stress within each individual layer.
2Reliability
If the floating gate thickness is maintained to preserve coupling ratio, then cross-talk based on parasitic capacitance between cell elements increases
Solution Approach 1:
The floating gate is divided into multiple thin layers, which reduces the lateral extent of charge distribution in each layer. This segmentation decreases parasitic capacitance between adjacent cell elements while maintaining the vertical coupling ratio through cumulative thickness. Each thin layer contributes to coupling without generating excessive cross-talk.
Solution Approach 2:
By distributing the gate thickness across multiple vertical layers rather than using a single thick lateral structure, the patent confines electric field lines more effectively within the vertical dimension. This reduces lateral electric field penetration that causes cross-talk between adjacent cells while preserving vertical coupling.
3Productivity
If the cell elements decrease in size, then the degree of integration increases, but the structure is highly apt to undergo mechanical stresses from various thin films deposited thereon
Solution Approach 1:
The multilayer floating gate structure divides the gate into multiple thin layers, which reduces mechanical stress within each individual layer. Each thin layer can better accommodate thermal expansion and deposition stresses from overlying films without cracking or delaminating, thereby maintaining structural integrity at high integration densities.
Solution Approach 2:
The patent changes the thickness parameter of each floating gate layer to be thin, which fundamentally alters the mechanical stress characteristics. Thin layers have lower intrinsic stress and better conformability to underlying structures, reducing the likelihood of stress-induced failures during subsequent film deposition processes.
4Device complexity
If a single layer floating gate is used, then the process is simple, but the threshold voltage distribution is wide
Solution Approach 1:
The floating gate is segmented into multiple thin layers, each contributing to the overall charge storage capability. This segmentation narrows threshold voltage distribution by creating more uniform electric fields and reducing variability in charge injection across the gate structure, while the layered fabrication process remains compatible with existing manufacturing techniques.
Solution Approach 2:
The multilayer floating gate structure acts as a composite structure where multiple thin layers work together to achieve superior electrical characteristics. The composite nature of the layered gate provides more consistent threshold voltage behavior compared to a single layer, while the fabrication process integrates seamlessly with conventional manufacturing.
Data Source
AI summary
Disclosed herein is a flash memory device in which the distribution of threshold voltage is significantly reduced and the durability is improved even though a floating gate has a micro- or nano-size length. It comprises a tunneling insulation film formed on a semiconductor substrate; a multilayer floating gate structure comprising a first thin storage electrode, a second thick storage electrode, and a third thin storage electrode, defined in that order on the tunneling insulation film; an interelectrode insulation film and a control electrode formed in that order on the floating gate structure; and a source/drain provided in the semiconductor substrate below the opposite sidewalls of the floating gate structure. The novel flash memory device can be readily fabricated at a high yield through a process compatible with a conventional one.