Multilayer FPC Board Signal Reflection Reduction
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Solution Overview
Problem
Conventional flexible printed circuit (FPC) board connections experience increased inductance and signal reflection at high frequencies, leading to jitter issues in optical modules, due to limitations in reducing inductance at the terminal portion between the FPC and printed circuit boards.
Innovation Solution
A multilayer FPC board structure with specific conductor and ground pad configurations, including first, second, and third signal pads and ground pads, connected via vias, forming a coplanar transmission line to achieve impedance matching and reduce reflection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the signal pad width is increased to reduce inductance and reflection, then signal quality improves, but the risk of short circuit with adjacent pads increases due to positional misalignment during soldering
Solution Approach 1:
The invention introduces a vertical dimension by stacking multiple conductor layers (first, second, and third conductor layers) with dielectric layers between them. The signal transmission path transitions from a single-layer wide pad to a multi-layer stacked pad structure, where the second signal pad in the second conductor layer provides the main signal path with reduced inductance, while the first and third signal pads in adjacent layers provide mechanical support and soldering interfaces without causing lateral short circuits.
Solution Approach 2:
The terminal portion is segmented into multiple conductor layers, with each layer containing signal pads and ground pads at different positions. The signal pads are divided into first, second, and third signal pads across different layers, allowing the signal path to be distributed vertically rather than requiring a single large horizontal pad area.
2Reliability
If the pad distance is reduced to minimize inductance, then signal quality improves, but the likelihood of short circuit between pads increases
Solution Approach 1:
The invention resolves the contradiction by moving the signal path to a different vertical layer (second conductor layer) where the second signal pad can be positioned with minimal distance to the transmission line, while the first and third signal pads in adjacent layers maintain adequate spacing to prevent short circuits during soldering.
3Ease of manufacture
If a two-layer FPC board structure is used, then manufacturing simplicity is maintained, but inductance reduction measures are limited due to constraints on pad width and distance
Solution Approach 1:
The invention transitions from a two-layer to a three-conductor-layer structure, adding vertical dimensionality to the circuit board design. This allows the second signal pad in the middle layer to serve as the primary signal path with optimized dimensions for low inductance, while the first and third layers provide support functions without interfering with the signal path optimization.
Solution Approach 2:
The terminal portion is segmented into multiple functional zones across different layers: the second signal pad and second ground pads in the second conductor layer handle high-speed signal transmission with minimized inductance, while the first and third signal pads in adjacent layers provide mechanical support and soldering interfaces.
Data Source
AI summary
A terminal portion configured to obtain electrical connection with a printed circuit board includes a first signal pad that is formed in a first conductor layer and is electrically separated from a ground layer, a pair of first ground pads that is formed in the first conductor layer to sandwich the first signal pad and is connected to the ground layer, a second signal pad that is formed in a second conductor layer and is connected to a signal line, a pair of second ground pads that is formed in the second conductor layer to sandwich the second signal pad and is electrically separated from the signal line, a third signal pad formed in a third conductor layer, and a pair of third ground pads formed in the third conductor layer to sandwich the third signal pad. The second signal pad is wider than the third signal pad.