Multi-Layer Fuse Array Layout for Reverse-Engineering Resistance
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Solution Overview
Problem
The existing electrical fuses in integrated circuits (ICs) are vulnerable to reverse engineering, which compromises the security of proprietary information stored in one-time programmable memory elements, as the resistance changes during programming can be reverse-engineered, allowing access to manufacturer codes and data.
Innovation Solution
The solution involves forming a layout structure of a memory array with a plurality of transistors and fuses, where each transistor is coupled with two serially or randomly connected fuses in different metal layers, ensuring that the programmed fuses are not in the same layer, making it difficult to reverse-engineer the manufacturer's proprietary code by distributing the burnt fuses across different metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fuses are used in a single metal layer for one-time programmable memory, then the manufacturing process is simple, but the security against reverse engineering is compromised
Solution Approach 1:
The patent extends the fuse structure from a single metal layer to multiple metal layers (at least two different metal layers). By distributing burnt fuses across different vertical layers, the invention creates a three-dimensional security mechanism that prevents reverse engineering through planar analysis, while maintaining compatibility with standard multi-layer CMOS fabrication processes
Solution Approach 2:
The patent divides the fuse array into multiple segments located in different metal layers. Each storage cell contains fuses distributed across at least two metal layers, so that the complete information cannot be obtained from any single layer. This segmentation prevents attackers from recovering proprietary code by analyzing just one metal layer, as the burnt fuse patterns are split across multiple separated segments
2Object-affected harmful factors
If fuses are distributed across multiple metal layers to prevent reverse engineering, then security is enhanced, but the device complexity increases
Solution Approach 1:
The patent employs standard multi-layer metal interconnect structures that are already universally used in CMOS integrated circuits for routing signals and power. By utilizing existing metal layers (such as M1, M2, M3, etc.) for fuse formation, the invention achieves multi-layer security without requiring additional specialized fabrication steps or unique structural elements, thus avoiding increased device complexity
Solution Approach 2:
The patent combines the fuse structure with the standard metal interconnect layers already present in the CMOS device. Rather than creating separate dedicated fuse layers, the invention merges the OTP memory function with the existing metal routing layers, allowing dual usage of these layers for both interconnection and fuse formation, thereby minimizing additional structural complexity
3Reliability
If resistance changes in fuses are used for data storage, then non-volatile memory function is achieved, but the resistance pattern becomes vulnerable to reverse engineering
Solution Approach 1:
The patent moves the storage of resistance change patterns from a two-dimensional planar distribution to a three-dimensional distribution across multiple metal layers. By stacking burnt fuse patterns vertically across at least two metal layers, the invention creates a volumetric code structure that cannot be decoded from any single planar view, thereby protecting proprietary information while maintaining the non-volatile memory function through resistance changes
Solution Approach 2:
The patent segments the resistance change pattern into multiple parts distributed across different metal layers. Each metal layer contains only a portion of the complete burnt fuse pattern, so that the full proprietary code information is not present in any single layer. This segmentation ensures that even if one layer is analyzed, the complete information remains protected, while the non-volatile storage function is maintained through the collective resistance states across all layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the security of the fuse array in ICs by making it challenging to obtain proprietary information through reverse engineering, as the burnt fuses are randomly distributed across different metal layers, thereby protecting the embedded data.
Implementation Method 1
The link is made of metal and arranged to connect the first pad and the second pad. The link has a substantially uniform cross-sectional area along a current flow direction between the first pad and the second pad. In the fourth metal layer, the width of the link is between 0.5 micrometer and 2 micrometer, and the length of the link is between 10 micrometer and 50 micrometer.
Data Source
AI summary
A method of forming a storage cell includes: forming a transistor on a semiconductor substrate; forming a plurality of fuses in at least one conductive layer on the semiconductor substrate to couple a connecting terminal of the transistor; forming a bit line to couple the plurality of fuses; and forming a word line to couple a control terminal of the transistor.