Multi-layer Gate Cap Structure for Semiconductor Contact Formation
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Solution Overview
Problem
In the fabrication of integrated circuits, the process of forming self-aligned contacts results in undesirable loss of protective gate cap layers and sidewall spacers, which complicates the formation of contact openings and increases the aspect ratio of the contact opening, making the gate etching and spacer etching processes more difficult.
Innovation Solution
A multi-layer gate cap structure is formed, comprising a first gate cap material layer, a high-k protection layer, and a second gate cap material layer, which provides enhanced protection to the gate structures and spacers during the contact formation process, reducing the consumption of protective materials and maintaining sufficient thickness to prevent undesirable attack during etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If self-aligned contacts are formed by removing dielectric material, then contact alignment accuracy is improved, but protective gate cap layers and sidewall spacers are consumed during etching
Solution Approach 1:
The gate cap structure is divided into multiple segments: original gate cap layer, first additional gate cap layer, and second additional gate cap layer. Each layer serves as a protective barrier during contact formation, distributing the protective function across multiple segments to prevent consumption of the original gate cap while maintaining self-aligned contact accuracy.
Solution Approach 2:
Additional gate cap layers are formed in advance before the contact etching process. These preliminary protective layers are deposited over the gate cap structure and sidewall spacers, ensuring that sufficient protective material is available before the harmful etching action occurs, thereby preventing unwanted consumption of critical protective materials.
2Reliability
If contact openings are formed through interlayer dielectric material, then electrical connections are established, but aspect ratio of contact openings increases making etching more difficult
Solution Approach 1:
The additional gate cap layers serve as intermediary protective structures between the etching process and the critical gate components. These intermediary layers allow the etching process to proceed through the interlayer dielectric to establish electrical connections while protecting against excessive aspect ratio formation and material consumption.
3Quantity of substance
If device dimensions are reduced to increase packing density, then transistor density is improved, but contact element dimensions become critical requiring extremely complex lithography and etch techniques
Solution Approach 1:
The invention changes the parameter of protective material thickness by adding multiple additional gate cap layers. This parameter change provides sufficient protective material thickness even when device dimensions are reduced, enabling contact formation in densely packed devices without requiring excessively complex lithography and etch techniques, as the enhanced protection allows for more robust processing.
Data Source
AI summary
One illustrative example of a transistor device disclosed herein includes, among other things, a gate structure, first and second spacers positioned adjacent opposite sides of the gate structure, and a multi-layer gate cap structure positioned above the gate structure and the upper surface of the spacers. The multi-layer gate cap structure includes a first gate cap material layer positioned on an upper surface of the gate structure and on the upper surfaces of the first and second spacers, a first high-k protection layer positioned on an upper surface of the first gate cap material layer and a second gate cap material layer positioned on an upper surface of the high-k protection layer. The first and second gate cap layers comprise different materials than the first high-k protection layer.