Multi-Layer Gate Dielectric for 2D Transistors
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Solution Overview
Problem
Conventional semiconductor fabrication processes face challenges in scaling down multi-gate transistors due to limitations in subthreshold swing and variability, making it difficult to extend into the 13 nm or sub-13 nm range, requiring new methodologies or technologies to enhance the performance and integration of thin-film transistors.
Innovation Solution
The integration of a bilayer gate dielectric structure comprising a low-k spacer and a high-k oxide layer, achieved through selective atomic layer deposition on metal contacts, which enhances the electrical performance of two-dimensional (2D) channel material-based transistors, and the introduction of a second gate to improve electrostatic control and reduce OFF-state leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional fabrication processes are used for multi-gate transistors, then manufacturing cost and compatibility with existing infrastructure are improved, but device performance and scalability to 13 nm or sub-13 nm range deteriorate due to subthreshold swing limitations and process variability
Solution Approach 1:
The patent changes the material parameters of the gate dielectric from conventional single-layer structures to multi-layer structures comprising high-k and low-k materials with specific dielectric constants. This parameter change enables achieving the required subthreshold swing performance (<60 mV/decade) while maintaining compatibility with existing fabrication processes, thus resolving the contradiction between ease of manufacture and device performance.
Solution Approach 2:
The patent employs composite gate dielectric structures combining high-k materials (such as HfO2, ZrO2) and low-k materials (such as SiO2, Si3N4) in specific layer configurations. This composite approach allows simultaneous optimization of electrostatic control (through high-k) and leakage reduction (through low-k), enabling scalability to 13 nm and sub-13 nm nodes while using conventional fabrication infrastructure.
2Device complexity
If single-layer gate dielectric structures are used, then device structure simplicity is improved, but electrostatic control and subthreshold swing performance deteriorate
Solution Approach 1:
The patent segments the gate dielectric into multiple functional layers: a high-k layer for enhancing electrostatic control and a low-k layer for reducing leakage and improving subthreshold swing. This segmentation allows each layer to perform its specific function optimally, achieving superior device reliability without excessive complexity, as the layered structure follows conventional fabrication sequences.
Solution Approach 2:
The patent applies different dielectric materials with specific properties at different locations within the gate stack. The high-k material is positioned where maximum electric field control is needed (adjacent to the channel), while low-k material is positioned for leakage control. This local quality differentiation optimizes electrostatic control and subthreshold swing performance while maintaining reasonable structural complexity.
3Productivity
If transistor dimensions are scaled down to increase device density, then capacity and integration density are improved, but process constraints and fabrication difficulty worsen
Solution Approach 1:
The multi-layer gate dielectric structure serves multiple functions simultaneously: enhancing electrostatic control, reducing leakage current, improving subthreshold swing, and enabling scalability to smaller nodes. This multi-functionality allows the same structure to address multiple performance requirements, reducing the need for additional complex process steps and thereby managing fabrication difficulty while increasing device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved subthreshold swing and ON/OFF ratio for thin-film transistors, increasing gate control and stability, thereby enhancing the performance and scalability of integrated circuit structures.
Implementation Method 1
selective atomic layer deposition on metal contacts
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E~2
AI summary
Thin film transistors having multi-layer gate dielectric structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a two-dimensional (2D) material layer above a substrate. A gate stack is over the 2D material layer, the gate stack having a first side opposite a second side, and the gate stack having a gate electrode around a gate dielectric structure. A first gate spacer is on the 2D material layer and adjacent to the first side of the gate stack. A second gate spacer is on the 2D material layer and adjacent to the second side of the gate stack, wherein the first gate spacer and the second gate spacer are continuous with a layer of the gate dielectric structure. A first conductive structure is coupled to the 2D material layer and adjacent to the first gate spacer. A second conductive structure is coupled to the 2D material layer and adjacent to the second gate spacer.