Multilayer Gate Electrodes With Etch-Stop Isolation for Mixed Dielectrics
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Solution Overview
Problem
Existing semiconductor devices face challenges in efficiently integrating multilayer gate and resistor structures, particularly in forming diverse gate dielectrics and electrodes that enhance performance and integration efficiency.
Innovation Solution
The semiconductor structure incorporates a combination of silicon oxide and metal oxide gate dielectrics, along with metallic and doped semiconductor gate electrodes, and includes methods for patterning and replacing gate materials to form complex gate structures and resistors, utilizing etch-stop layers and planarization processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple gate dielectric materials (silicon oxide and metal oxide) are integrated in a single device, then device performance and functionality are enhanced, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The gate dielectric is segmented into multiple distinct layers: a silicon oxide gate dielectric layer and a metal oxide gate dielectric layer. Each layer can be independently formed, patterned, and processed, allowing different regions of the device to have different dielectric configurations without requiring complete redesign of the manufacturing process. This segmentation enables first field effect transistors to use one dielectric type while second field effect transistors use another.
Solution Approach 2:
Different gate dielectric materials are applied to different regions of the semiconductor substrate based on local device requirements. First field effect transistors receive a silicon oxide gate dielectric, while second field effect transistors receive a metal oxide gate dielectric. This local differentiation allows optimization of each transistor type's performance characteristics without affecting other regions, resolving the contradiction between versatility and manufacturing complexity.
2Reliability
If diverse gate electrode structures (metallic and doped semiconductor) are formed, then electrical properties and device performance are improved, but fabrication steps and process time increase
Solution Approach 1:
A doped semiconductor gate electrode layer is formed preliminarily across the entire substrate before metallic gate electrode deposition. This preliminary layer serves as a foundation that can be selectively retained or removed in different regions. By establishing this base layer early in the process, the subsequent formation of different gate electrode types (metallic vs. doped semiconductor) is simplified, reducing overall fabrication time while maintaining electrical performance.
Solution Approach 2:
The doped semiconductor gate electrode material is selectively removed from regions where metallic gate electrodes will be formed, while being retained in regions where doped semiconductor gates are desired. This extraction approach allows efficient creation of diverse gate structures from a unified preliminary layer, minimizing additional fabrication steps and reducing process time while achieving the desired electrical properties.
3Productivity
If complex multilayer gate structures are integrated with resistor structures, then integration efficiency is enhanced, but patterning difficulty and manufacturing precision requirements increase
Solution Approach 1:
The gate electrode structures serve multiple functions: they act as gates for field effect transistors and simultaneously serve as electrodes for resistor structures. The same metallic gate electrode layer and doped semiconductor gate electrode layer are used for both transistor gate functionality and resistor electrode functionality. This multi-functionality enables integration of complex structures without requiring separate dedicated layers, thereby improving productivity while managing patterning precision requirements through shared process steps.
Data Source
AI summary
Semiconductor devices that include a replacement metallic gate electrode and a gate-level semiconductor structure can be formed on a seme semiconductor substrate by providing an etch-stop structure that prevents replacement of the gate-level semiconductor structure, and by replacing a sacrificial semiconductor gate electrode with the replacement metallic gate electrode. The gate-level semiconductor structure may include a semiconductor gate electrode of a field effect transistor, or a semiconductor material strip that can be employed as a resistor. In one embodiment, the etch-stop structure and an overlying sacrificial structure may be replaced with another replacement metallic gate electrode. In another embodiment, a silicide region may be formed on the semiconductor gate electrode.