Multilayer Gate Insulator for Thin Film Transistor CVD Defects
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Solution Overview
Problem
The formation of foreign matter during the CVD film deposition process in amorphous silicon thin film transistors leads to yield loss due to abnormal SiNx film formation, point defects, line defects, and Electrostatic Discharge (ESD) in the BCE process.
Innovation Solution
A thin film transistor structure with a multilayer gate insulating layer, comprising a first layer deposited at a low rate, a second layer deposited at a high rate, and a third layer deposited at a low rate, where the first and third layers have higher density than the second layer, is used to prevent foreign matter formation, improving the interface quality and electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the flow rate of SiH4 is increased to improve deposition speed, then productivity is improved, but foreign matter formation occurs due to insufficient decomposition of SiH4
Solution Approach 1:
The gate insulating layer is divided into multiple sub-layers with different deposition rates. The first sub-layer is deposited at a low rate to ensure complete decomposition and avoid foreign matter, while the second sub-layer is deposited at a high rate to maintain productivity. This segmentation allows each layer to serve its specific function without compromising the other.
Solution Approach 2:
The deposition rate parameter is changed across different sub-layers. The first sub-layer uses a low deposition rate (first parameter range) to prevent foreign matter formation, while the second sub-layer uses a high deposition rate (second parameter range) to improve productivity. This parameter variation resolves the contradiction between speed and quality.
2Device complexity
If a single-layer gate insulating layer is used to simplify the structure, then device complexity is reduced, but foreign matter formation occurs due to high deposition rate requirements
Solution Approach 1:
The gate insulating layer is segmented into multiple sub-layers with different deposition characteristics. The first sub-layer is deposited at a low rate to prevent foreign matter, while the second sub-layer is deposited at a high rate for productivity. This segmentation resolves the contradiction between structural simplicity and foreign matter prevention.
3Productivity
If the deposition rate is increased to improve manufacturing efficiency, then productivity is improved, but film quality deteriorates due to abnormal SiNx formation
Solution Approach 1:
The gate insulating layer is divided into sub-layers with different deposition rates. The first sub-layer uses a low deposition rate to ensure high film quality and complete decomposition, while the second sub-layer uses a high deposition rate to improve manufacturing efficiency. This segmentation allows both quality and efficiency to be optimized in different layers.
Solution Approach 2:
The deposition rate parameter is varied across sub-layers. The first sub-layer uses a low deposition rate parameter to ensure film quality, while the second sub-layer uses a high deposition rate parameter to improve efficiency. This parameter change strategy resolves the contradiction between manufacturing precision and productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces foreign matter generation, enhances electron mobility, and improves the overall performance and yield of the thin film transistor by ensuring a stable and efficient film deposition process.
Implementation Method 1
decomposition of SiH4 is insufficient, resulting in the formation of foreign matter (Particle) due to formation of abnormal SiNx (non-ideal SiNx thin film), and point defect, line defect, Electrostatic Discharge (ESD), and the like, caused by the foreign matter formed by Chemical Vapor Deposition (CVD) film deposition
Data Source
AI summary
Disclosed are a thin film transistor, a method of manufacturing the same, and an array substrate. The thin film transistor includes a substrate, a gate, a gate insulating layer, an active layer, an ohmic contact layer, and a source-drain electrode layer, the gate insulating layer includes at least a first gate insulating layer deposited at a low rate, a second gate insulating layer deposited at a high rate, and a third gate insulating layer deposited at a low rate, the first gate insulating layer is in contact with the gate, the third gate insulating layer is in contact with the active layer, and the first gate insulating layer and the third gate insulating layer have a density greater than a density of the second gate insulating layer.