Multi-Layer Gate Spacer Structure for FinFET Gate Uniformity
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Solution Overview
Problem
The challenge in fabricating multi-gate transistors, such as FinFETs, lies in protecting the dummy gate during gate replacement processes, as insufficient protection can lead to nonuniformity and height loss of the gate structures, resulting in defects and yield impact.
Innovation Solution
A multi-layer gate spacer structure is introduced, comprising a low-k dielectric first spacer layer and a second spacer layer with alternating silicon and nitrogen-containing sublayers, formed using atomic layer deposition, which provides additional protection by redepositing polymeric byproducts during etching, maintaining gate profile uniformity and preventing shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single-layer gate spacer is used to protect the dummy gate, then the fabrication process is simple, but the protection is insufficient leading to nonuniformity and height loss of gate structures
Solution Approach 1:
The gate spacer is divided into multiple layers: a first gate spacer layer (e.g., silicon oxide) and a second gate spacer layer (e.g., silicon nitride). Each layer provides different protective functions, with the second layer offering enhanced protection during etching processes. This segmentation allows the structure to maintain better profile uniformity and prevent height loss while managing complexity through functional differentiation.
Solution Approach 2:
The gate spacer employs composite material structure combining different dielectric materials with complementary properties. The first layer (silicon oxide) provides baseline protection and compatibility, while the second layer (silicon nitride) offers superior etch resistance. This composite approach enhances overall protection capability and gate profile uniformity without requiring a single complex material.
2Reliability
If the dummy gate is not adequately protected during etching, then the fabrication process is fast, but the gate structures suffer from height loss and nonuniformity causing defects
Solution Approach 1:
The multi-layer gate spacer structure is formed in advance before the critical etching processes. The first and second gate spacer layers are deposited and configured to provide predetermined protection levels. This preliminary preparation ensures that when etching occurs, the dummy gate and subsequent gate structures are already protected, preventing height loss and nonuniformity while maintaining process flow efficiency.
Solution Approach 2:
The second gate spacer layer (e.g., silicon nitride) acts as a cushioning protective layer that absorbs and mitigates the harmful effects of etching processes. This layer is specifically designed to provide enhanced protection during source/drain recess etching and gate material deposition, preventing damage to the dummy gate and ensuring uniform gate structure formation, thereby improving reliability without significantly impacting productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively protects the dummy gate, ensuring uniformity and preventing shorts between the gate and source/drain features, thereby enhancing the fabrication process and yield of multi-gate transistors.
Implementation Method 1
a second spacer layer with alternating silicon and nitrogen-containing sublayers, formed using atomic layer deposition, which provides additional protection by redepositing polymeric byproducts during etching
Implementation Method 2
a second spacer layer with alternating silicon and nitrogen-containing sublayers, formed using atomic layer deposition
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region, forming a dummy gate stack over the channel region of the semiconductor element, depositing a first spacer layer over sidewalls of the dummy gate stack, depositing a second spacer layer over the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer, after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess, and after the etching, removing the second spacer layer.