Multilayer Carbon-Rich Gate Spacers for Low Parasitic Capacitance
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Solution Overview
Problem
Conventional low-k spacer materials for semiconductor devices are susceptible to moisture, oxidation, and metal diffusion, leading to instability and high dielectric constants, which contribute to parasitic capacitance and capacitive coupling issues as semiconductor devices shrink to smaller dimensions.
Innovation Solution
A method involving the deposition of multiple thin layers of carbon-rich materials with intermediate nitrogen plasma treatment to create ultra-low k gate spacers, providing improved conformal coverage, etch selectivity, and stability, with a dielectric constant less than 4.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional low-k spacer materials are used, then the dielectric constant is reduced, but the materials become susceptible to moisture, oxidation, and metal diffusion leading to instability
Solution Approach 1:
The patent uses a composite material system consisting of multiple alternating layers of carbon-rich low-k material (with k<4.0) and nitrogen-containing stabilizing material. This composite structure combines the low dielectric constant property of carbon-rich materials with the stability provided by nitrogen-containing materials, resolving the contradiction between reducing parasitic capacitance and maintaining reliability during downstream processing
Solution Approach 2:
The patent applies different materials with different properties to different layers of the spacer structure. The carbon-rich layers provide low-k properties while the nitrogen-containing layers provide stability and resistance to moisture and oxidation. This local differentiation of material properties allows each layer to optimize its specific function, achieving both low parasitic capacitance and high reliability
2Productivity
If semiconductor devices are shrunk to smaller dimensions, then device density is improved, but parasitic capacitance and capacitive coupling issues increase
Solution Approach 1:
The patent changes the dielectric constant parameter of the spacer material by using carbon-rich low-k material with k<4.0, which is significantly lower than conventional materials. This parameter change directly reduces parasitic capacitance and capacitive coupling effects, allowing device scaling to proceed without the harmful electrical interactions that typically increase as devices shrink
3Manufacturing precision
If multiple thin layers are deposited with intermediate plasma treatment, then conformal coverage and etch selectivity are improved, but process complexity increases
Solution Approach 1:
The patent segments the spacer formation process into multiple thin alternating layers of carbon-rich material and nitrogen-containing material, with intermediate nitrogen plasma treatment steps. This segmentation allows each thin layer to be deposited with high conformal coverage and the plasma treatment to provide etch selectivity. While the process has multiple steps, each step is relatively simple and can be performed using standard PECVD and plasma equipment, making the complexity manageable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in stable, ultra-low k gate spacers that reduce parasitic capacitance and capacitive coupling, maintaining stability during downstream processing and enabling efficient electrical current flow in semiconductor devices.
Implementation Method 1
performing a first nitrogen plasma treatment process on the first spacer layer to increase a density of the first spacer layer
Implementation Method 2
depositing a first spacer layer on a sidewall of the gate stack by a first plasma enhanced chemical vapor deposition (PECVD) method
Data Source
AI summary
A method of making a semiconductor device includes forming a gate stack on a substrate. The method further includes depositing a first spacer layer on a sidewall of the gate stack. The first spacer layer includes silicon and carbon. The method includes performing a first nitrogen plasma treatment process on the first spacer layer to increase a density of the first spacer layer. The method further includes depositing a second spacer layer on the first spacer layer. The second spacer layer includes silicon, carbon, and nitrogen.