Multilayer High-k Gate Dielectric for FinFET Gate Control
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Solution Overview
Problem
Conventional gate oxide scaling limits the inversion charge and reliability in sub-10 nm transistor technology nodes, necessitating new methodologies for further miniaturization and performance optimization in integrated circuits.
Innovation Solution
A multilayer high-k gate dielectric structure is introduced, comprising a first and second high-k material with modified properties such as ferroelectricity, crystalline phase, or strain, integrated with a metal gate electrode, enabling increased gate control and inversion charge in non-planar transistors like FinFETs, and utilizing SOI template formation for high-performance and low-leakage transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional gate oxide scaling is used to reduce transistor size, then device density increases, but inversion charge and reliability deteriorate
Solution Approach 1:
The patent employs a composite gate dielectric structure consisting of multiple high-k material layers (e.g., hafnium oxide, zirconium oxide, titanium oxide) with different dielectric properties. This composite approach enables achieving higher inversion charge and reliability while maintaining scaled transistor dimensions, as each layer contributes different electrical characteristics that collectively overcome the limitations of conventional single-material gate oxides
Solution Approach 2:
The patent modifies the dielectric constant (k-value) parameter by transitioning from conventional low-k gate oxide materials to high-k materials. This parameter change allows maintaining thicker effective gate oxide equivalents for better reliability while keeping physical thickness scaled down for high density, thereby resolving the contradiction between size reduction and performance maintenance
2Productivity
If gate oxide thickness is reduced to increase device density, then transistor scaling improves, but gate control and reliability worsen
Solution Approach 1:
The multilayer high-k structure provides enhanced gate control through the combined effect of multiple dielectric layers with optimized thicknesses and material properties. This composite configuration maintains effective gate control over the channel even at scaled dimensions, preventing the degradation that would occur with simple thinning of conventional gate oxides
Solution Approach 2:
The patent transitions from a single-layer gate dielectric to a vertically stacked multilayer structure. This dimensional change in the gate dielectric architecture enables achieving both high device density and reliable gate control by distributing the dielectric function across multiple layers rather than relying on a single thin layer
3Manufacturing precision
If new fabrication methodologies are introduced for sub-10 nm nodes, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming individual high-k material layers through sequential deposition, modifying specific layers with plasma or chemical treatments, and selective etching. This segmentation of the complex multilayer fabrication into manageable steps enables precise control of each layer's properties while maintaining overall process feasibility
4Reliability
If multilayer high-k gate dielectric is used to increase inversion charge, then transistor performance improves, but device complexity increases
Solution Approach 1:
Different layers within the gate dielectric stack are assigned specific local qualities - some layers provide high dielectric constant for charge storage, others provide interface quality for carrier mobility, and some provide barrier properties. This local optimization of each layer's function enables achieving high inversion charge while managing the complexity through purposeful material differentiation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multilayer high-k gate dielectric structure enhances gate control, stability, and performance by increasing gate oxide thickness scaling and inversion charge, overcoming conventional limitations and enabling high-performance logic transistors for future technology nodes.
Implementation Method 1
An inversion layer is formed in the semiconductor substrate via capacitive coupling when a gate bias is applied.
Implementation Method 2
a gate oxide is a dielectric/insulating layer that separates the gate terminal of the transistor from the underlying source and drain terminals
Data Source
AI summary
A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack. A selector element is above the metal layer.