Multilayer On-Chip Inductor Layout for Higher Q Without Added Cost
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in achieving high Q value for on-chip inductors due to the use of thinner inductor traces in digital or baseband circuits, which compromises the performance of radio frequency circuits.
Innovation Solution
A multilayer-type on-chip inductor structure is designed with symmetrically arranged winding portions in inter-metal dielectric and insulating redistribution layers, featuring semi-circular stacking layers and slit openings to increase the cross section of the inductor, utilizing thicker trace layers to enhance the Q value without additional manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If thinner inductor traces are used in digital or baseband circuits, then manufacturing cost is reduced, but Q value decreases
Solution Approach 1:
The patent transitions from planar 2D trace layouts to a 3D multilayer stacked configuration. Multiple semi-circular stacking layers are arranged vertically across different metal layers (e.g., first metal layer, second metal layer), creating a three-dimensional inductor structure that increases the effective cross-section and Q value without requiring thicker individual traces or additional manufacturing processes
Solution Approach 2:
The patent implements nested semi-circular stacking layers where inner semi-circular traces are surrounded by outer semi-circular traces in a concentric arrangement. Each stacking layer contains multiple semi-circular traces nested within each other, maximizing the use of available space and increasing the inductor's effective area and Q value within the same footprint
2Reliability
If thicker trace layers are used to increase Q value, then inductor performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent makes existing metal layers and inter-metal dielectric layers serve dual purposes: they continue to function as standard interconnect structures for signal routing while simultaneously forming the inductor structure. The semi-circular stacking layers are created using the same fabrication processes as standard planar inductors, eliminating the need for additional manufacturing steps or specialized thick-trace processes
Solution Approach 2:
The inductor is segmented into multiple discrete semi-circular stacking layers distributed across different metal layers. Each stacking layer consists of multiple semi-circular traces that can be independently formed using standard photolithography and metallization processes. This segmentation allows the complex 3D structure to be built incrementally using existing manufacturing capabilities
Data Source
AI summary
A multilayer-type on-chip inductor with a conductive structure includes an insulating redistribution layer disposed on an inter-metal dielectric (IMD) layer, and first and second winding portions symmetrically arranged in the IMD layer and the insulating redistribution layer with respect to a symmetrical axis. The first and second winding portions each includes at least first and second semi-circular stacking layers arranged from the inside to the outside and in concentricity. The first and second semi-circular stacking layers each has a first trace layer in the insulating redistribution layer and a second trace layer in the IMD layer and correspondingly formed below the first trace layer. A first slit opening passes through the second trace layer and extends in the extending direction of the length of the second trace layer.