Multi-Layer Inner Spacers for Low-Capacitance Multi-Gate Transistors
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Solution Overview
Problem
As semiconductor technology advances to sub-10 nm technology nodes, existing low-k materials used as inner spacers in multi-gate transistors suffer from etching loss during the replacement gate process, leading to increased stray capacitance and reduced device performance.
Innovation Solution
The implementation of multi-layer inner spacers comprising a low-k dielectric layer and a capping layer that protects the low-k dielectric layer from etching loss, reducing gate-to-drain and gate-to-source capacitance, and allowing for precise control of spacer thickness, shape, and location.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If low-k materials are used as inner spacers, then stray capacitance is reduced, but etching loss occurs during replacement gate process
Solution Approach 1:
The patent applies composite materials by combining low-k dielectric material with a capping layer material to form a multi-layer inner spacer structure. The low-k layer reduces stray capacitance while the capping layer protects it from etching loss during the replacement gate process, resolving the contradiction between reducing harmful capacitance and preventing material loss.
Solution Approach 2:
The capping layer acts as an intermediary protective layer that shields the low-k dielectric material from the etching process. This mediator allows the low-k material to maintain its capacitance-reducing function while being protected from direct exposure to etchants during gate replacement.
2Ease of manufacture
If single-layer inner spacers are used, then fabrication is simpler, but control of spacer thickness, shape, and location is imprecise
Solution Approach 1:
The inner spacer is segmented into multiple functional layers: a low-k dielectric layer for capacitance reduction and a capping layer for protection. This segmentation allows each layer to be optimized for its specific function while maintaining precise control over the overall spacer structure's thickness, shape, and location through independent layer fabrication parameters.
3Productivity
If multi-gate structures are implemented, then device density and performance are improved, but gate control over channel region is insufficient
Solution Approach 1:
The patent transitions from planar single-gate structures to three-dimensional multi-gate structures (FinFET or GAA) where the gate electrode wraps around the channel region from multiple directions. This dimensional change enables the gate to control the channel from top, bottom, and sidewalls, significantly improving gate control and reducing short-channel effects while maintaining high device density.
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked; forming a sacrificial gate structure over the fin structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming an S/D space; laterally etching the first semiconductor layers through the S/D space, thereby forming recesses; forming a first insulating layer, in the recesses, on the etched first semiconductor layers; after the first insulating layer is formed, forming a second insulating layer, in the recesses, on the first insulating layer, wherein a dielectric constant of the second insulating layer is less than that of the first insulating layer; and forming an S/D epitaxial layer in the S/D space, wherein the second insulating layer is in contact with the S/D epitaxial layer.