Multilayer Insulating Spacer for Leakage Prevention in Scaled Transistors
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Solution Overview
Problem
In highly down-scaled transistors, the etch resistance of layers for electrically insulating gate lines is insufficient, leading to increased leakage currents and electrical short circuits, which affects the reliability and performance of semiconductor devices.
Innovation Solution
A multilayer-structured insulating spacer is introduced, comprising an oxide layer and carbon-containing insulating layers with different carbon contents, positioned between the gate line and the contact plug to provide optimal etch resistance and prevent leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-layer insulating spacer is used, then the device structure is simple, but the etch resistance is insufficient leading to leakage currents
Solution Approach 1:
The insulating spacer is divided into multiple layers with different materials and functions. The first insulating layer (e.g., silicon oxide) provides baseline insulation, while the second insulating layer (e.g., silicon nitride or silicon oxynitride) provides enhanced etch resistance. This segmentation allows each layer to be optimized for its specific function, resolving the contradiction between simplicity and performance.
Solution Approach 2:
The insulating spacer uses a composite structure combining different insulating materials with complementary properties. The combination of silicon oxide and silicon nitride/oxynitride creates a composite spacer that achieves superior etch resistance and electrical insulation compared to single-layer structures, while maintaining reasonable fabrication complexity.
2Length of moving object
If the gate length is reduced, then the transistor size is miniaturized, but the etch resistance becomes insufficient
Solution Approach 1:
As gate length is reduced for miniaturization, the insulating spacer is segmented into multiple layers to compensate for the reduced dimensional buffer. The multi-layer structure ensures that even with smaller overall dimensions, the critical etch resistance function is maintained through the combined protective effect of multiple material layers.
Solution Approach 2:
The multi-layer insulating spacer structure provides locally optimized properties: the first layer provides general insulation while the second layer specifically targets etch resistance at critical interfaces. This local quality differentiation ensures reliable performance in miniaturized devices where every nanometer counts.
3Reliability
If the insulating layer provides high etch resistance, then leakage currents are prevented, but the dielectric constant increases
Solution Approach 1:
The insulating function is segmented between two layers: the first layer (silicon oxide) provides good electrical insulation with moderate dielectric constant, while the second layer (silicon nitride/oxynitride) provides etch resistance with controlled dielectric constant. This segmentation allows the overall structure to achieve low leakage current while managing the total dielectric constant through material selection and thickness optimization.
Data Source
AI summary
A device includes: a gate line on an active region of a substrate, a pair of source/drain regions in the active region on both sides of the gate line, a contact plug on at least one source/drain region out of the pair of source/drain regions; and a multilayer-structured insulating spacer between the gate line and the contact plug. The multilayer-structured insulating spacer may include an oxide layer, a first carbon-containing insulating layer covering a first surface of the oxide layer adjacent to the gate line, and a second carbon-containing insulating layer covering a second surface of the oxide layer, opposite to the first surface of the oxide layer, adjacent to the contact plug.