Multilayer Interconnect Structure for Embedded Semiconductor Devices
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Solution Overview
Problem
Current electronics packaging methods, such as wire bond and flip chip technologies, face challenges in achieving high performance and yield due to limitations in interconnect parasitics, defects, and compatibility with high I/O count and high power semiconductor devices.
Innovation Solution
A multilayer interconnect structure with insulating substrate layers and conductive wiring layers, featuring microvias for direct electrical connections, is used to embed semiconductor devices after testing, minimizing interconnect processing and utilizing different connection types for signal and power/ground pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire bond technology is used to connect semiconductor devices to interconnect structures, then the packaging approach is low cost and mature, but the electrical performance is poor with high inductance and series resistance
Solution Approach 1:
The patent extracts and eliminates the wire bond interconnect element from the packaging system. Instead of using wire bonds to connect device pads to substrate pads, the invention directly attaches the semiconductor device to a multilayer interconnect structure that has conductive pathways embedded within it, thereby removing the high-inductance wire bond from the signal path while maintaining manufacturing feasibility
Solution Approach 2:
The patent transitions from a two-dimensional wire bond connection (surface-mounted wire) to a three-dimensional embedded conductive pathway within the multilayer substrate. The conductive paths are routed through internal layers of the substrate, creating shorter and more direct electrical pathways that reduce inductance and series resistance while keeping the device attachment planar
2Ease of manufacture
If wire bonds are used for I/O connections, then the bonding process is established, but current crowding on bond pads and microcracking within semiconductor devices occur
Solution Approach 1:
The invention removes the wire bond attachment process entirely, eliminating the mechanical stress and current crowding effects that occur at wire bond pad interfaces. The semiconductor device is instead attached directly to the substrate using established die attach techniques, and electrical connections are made through embedded conductive pathways that do not concentrate current at discrete bond pad locations
Solution Approach 2:
The patent distributes current flow from concentrated bond pad locations to distributed pathways within the substrate layers. The conductive paths are embedded throughout the substrate thickness and routed through multiple internal layers, spreading the current density and eliminating the current crowding phenomenon that occurs at wire bond attachment points
3Quantity of substance
If flip chip with solder bumps is used, then I/O pad capacity increases to 5× to 20× more pads than wire bond, but solder has poor electrical conductivity and is susceptible to solder fatigue and electro-migration failures
Solution Approach 1:
The patent extracts and eliminates the solder bump interconnect element from the packaging system. Instead of using solder bumps to connect device pads to substrate pads, the invention directly attaches the semiconductor device to a multilayer interconnect structure with embedded conductive pathways, thereby removing the reliability issues associated with solder (poor conductivity, fatigue, electro-migration) while maintaining high I/O pad capacity
Solution Approach 2:
The patent uses composite interconnect structures within the multilayer substrate that combine different conductive materials and pathways. The embedded conductive paths may use high-conductivity materials such as copper or aluminum in specific layers, combined with appropriate barrier and adhesion layers, creating a composite structure that provides both high electrical conductivity and resistance to failure mechanisms while supporting high I/O densities
4Productivity
If semiconductor devices are attached to interconnect structures before testing, then manufacturing efficiency increases, but defects in the interconnect structure cause scrapping of good semiconductor devices
Solution Approach 1:
The patent performs the semiconductor device attachment to the interconnect structure after the device has been tested and verified functional. This preliminary testing of the device before final assembly ensures that only good devices are committed to the interconnect structure, preventing the scrapping of functional devices due to interconnect defects while maintaining manufacturing efficiency through a streamlined post-attachment process
Data Source
AI summary
An electronics package is disclosed that comprises a multilayer interconnect structure including a plurality of insulating substrate layers each having a plurality of microvias formed therein, a plurality of conductive wiring layers positioned on the plurality of insulating substrate layers, and a plurality of conductive microvias in the plurality of microvias to, wherein a bottom wiring layer includes a plurality of first terminal pads that are positioned on a bottom surface of the multilayer interconnect structure. The electronics package also comprises an electrical component coupled to the bottom surface of the multilayer interconnect structure, the electrical component including first I/O pads aligned with the first terminal pads and second I/O pads aligned to regions of the multilayer interconnect structure without first terminal pads. The electronics package further comprises a plurality of conductive through vias extending through the multilayer interconnect structure and electrically connected to the plurality of second I/O pads.