Multilayer Interconnect Wiring Structure for Low-Resistance IC Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As integrated circuit devices downscale, the resistance of metal wiring layers increases, compromising electrical characteristics and reliability due to finer line widths and pitches, necessitating a solution to suppress resistance and enhance performance.
Innovation Solution
The integration of a multi-layered wiring structure with specific precursor materials and grain sizes in the interconnect wiring layers, where the second interconnect wiring layer has a larger crystal grain size and lacks oxygen, reducing electrical resistance and improving structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If metal wiring layers are downscaled to achieve finer line widths and pitches, then device integration density is improved, but electrical resistance of the wiring layers increases
Solution Approach 1:
The patent employs a composite wiring structure consisting of multiple metal layers (first and second interconnect wiring layers) with different material compositions and crystal grain characteristics. This composite approach allows the system to achieve both fine pitch scaling and low resistance by combining the advantages of different metal materials in a multi-layer configuration
Solution Approach 2:
The patent applies local quality by creating distinct regions within the wiring structure with different properties. Specifically, the first interconnect wiring layer has smaller crystal grains optimized for one set of electrical characteristics, while the second interconnect wiring layer has larger crystal grains optimized for low resistance, allowing each layer to perform its specific function optimally
2Device complexity
If a single-layer wiring structure is used, then manufacturing process is simpler, but resistance control and electrical characteristics are insufficient
Solution Approach 1:
The patent segments the wiring function into multiple independent layers, where each layer (first interconnect wiring layer and second interconnect wiring layer) has distinct material properties and crystal grain sizes. This segmentation allows independent optimization of each layer for specific electrical characteristics while maintaining overall system performance
Solution Approach 2:
The patent transitions from a single-layer (2D) wiring structure to a multi-layer (3D) wiring architecture. By adding the vertical dimension with stacked wiring layers, the system achieves superior resistance control and electrical characteristics without excessively complicating the manufacturing process, as each layer can be formed using sequential deposition processes
Data Source
AI summary
An integrated circuit device may include a source/drain contact insulation layer on a lower structure, a source/drain contact via penetrating through the source/drain contact insulation layer, an interconnect wiring insulation layer on the source/drain contact insulation layer and including an interconnect wiring trench exposing a top surface of the source/drain contact via, a first interconnect wiring layer covering a lower portion of a sidewall of the interconnect wiring trench and including a first precursor, and a second interconnect wiring layer on the first interconnect wiring layer. The second interconnect wiring layer may cover an upper portion of a sidewall of the interconnect wiring trench and may include a second precursor. A crystal grain size of the second precursor may be larger than a crystal grain size of the first precursor.