Multi-Layer Interconnect Structure for Precise Metal Line Etching
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Solution Overview
Problem
The increasing density and decreasing dimensions of semiconductor components pose challenges in the etching process for forming metal lines, leading to difficulties in metal contact and line formation.
Innovation Solution
A multi-layer conductive structure is formed with specific thicknesses and materials for each layer, including a thin first conductive layer acting as an etch stop, a second conductive layer with high etch selectivity, and a third conductive layer providing protection during patterning, along with a hard mask structure for precise patterning and minimal damage to underlying layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are continuously scaled down to increase density, then transistor density and device packing increase, but the difficulty of the etching process to form metal lines increases
Solution Approach 1:
The patent applies segmentation by dividing the single etching process into multiple sequential etching operations with different selectivity ratios. The interconnect structure is formed through a first etching process with lower selectivity followed by a second etching process with higher selectivity, allowing precise control at each stage despite reduced feature sizes.
Solution Approach 2:
The patent changes the selectivity parameter of the etching process by using different etching conditions and mask configurations for sequential etching steps. The first etching process uses one set of selectivity parameters while the second etching process uses different selectivity parameters, enabling adaptive control as dimensions scale down.
2Area of stationary object
If device dimensions are scaled down, then area occupied by devices decreases, but the distances between metal contacts or metal lines become much shorter making etching more difficult
Solution Approach 1:
The patent segments the metal line formation into multiple etching stages, where each stage creates portions of the final interconnect structure. This segmentation allows precise control over short distances between features by adjusting etching parameters independently for each stage.
Solution Approach 2:
The first etching process performs preliminary action by creating initial openings and structures before the second etching process refines the final dimensions. This preliminary etching establishes a foundation that guides subsequent high-precision etching steps.
3Device complexity
If a single etching process is used, then the manufacturing process is simpler, but damage to dielectric materials and conductive features increases
Solution Approach 1:
The patent divides the etching process into multiple sequential steps, each with optimized selectivity ratios tailored to specific removal tasks. This segmentation reduces damage by limiting the aggressiveness of each individual etching step compared to a single high-selectivity process.
Solution Approach 2:
The patent applies different selectivity qualities to different etching steps based on local requirements. The first etching process uses selectivity optimized for removing dielectric material, while the second etching process uses selectivity optimized for removing conductive features, ensuring minimal damage in each local context.
4Manufacturing precision
If etching selectivity is increased to improve patterning precision, then manufacturing precision improves, but damage to underlying layers increases
Solution Approach 1:
The patent segments the high-selectivity etching into a second process that occurs after preliminary structuring. This allows the high selectivity to be applied only where needed for final precision without exposing underlying layers to prolonged aggressive etching conditions.
Solution Approach 2:
The first etching process performs preliminary action by removing bulk dielectric material with lower selectivity, establishing the basic structure before the second high-selectivity etching process refines the pattern. This preliminary removal reduces the burden on the second process, limiting its exposure time and damage potential.
Data Source
AI summary
An interconnect structure includes a dielectric layer, a first conductive feature, a second conductive feature, a third conductive feature, and a dielectric fill. The first conductive feature is disposed in the dielectric layer. The second conductive feature is disposed over the first conductive feature. The second conductive feature includes a first conductive layer disposed over the first conductive feature, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer. The first conductive layer, the second conductive layer and the third conductive layer have substantially the same width. The third conductive feature is disposed over the dielectric layer. The dielectric fill is disposed over the dielectric layer between the second conductive feature and the third conductive feature.