Multi-Layer Interconnect Structure for Lower Sheet Resistance
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Solution Overview
Problem
As semiconductor device dimensions decrease, achieving improved sheet resistance becomes a challenge due to limitations in defining structures photo-lithographically, necessitating innovative approaches for enhanced semiconductor devices.
Innovation Solution
The development of an interconnect structure with conductive features extending through multiple dielectric layers, where one conductive feature has a greater top critical dimension and height than another, reducing capacitance and electrical resistance by optimizing the arrangement and formation of conductive features within the semiconductor device structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor device dimensions are reduced to increase density, then device functionality and performance improve, but sheet resistance deteriorates and manufacturing precision becomes more difficult to achieve
Solution Approach 1:
The patent applies dimensionality change by forming conductive features that extend through multiple dielectric layers (vertical dimension) rather than being confined to a single layer. This multi-layer conductive structure increases the effective conductive cross-section area, thereby improving sheet resistance without requiring further reduction in lateral dimensions, thus resolving the contradiction between device density and sheet resistance.
2Reliability
If conductive features are made smaller to reduce capacitance, then electrical performance improves, but manufacturing precision becomes more difficult
Solution Approach 1:
The patent transitions from two-dimensional conductive features to three-dimensional conductive structures that extend vertically through multiple dielectric layers. This dimensional change allows the conductive features to maintain larger lateral dimensions (easier to manufacture) while achieving reduced capacitance through optimized vertical positioning and spacing between layers.
Solution Approach 2:
The conductive features are nested across multiple dielectric layers, with conductive elements positioned in different vertical planes. This nesting arrangement reduces the effective capacitive coupling between adjacent conductors by increasing their vertical separation, thereby reducing capacitance while maintaining manufacturable lateral dimensions.
3Adaptability or versatility
If conductive features are arranged more densely to improve routing, then device functionality improves, but contact resistance increases
Solution Approach 1:
The patent utilizes the vertical dimension by forming conductive features that span multiple dielectric layers, creating additional routing pathways in the vertical direction. This multi-layer approach increases routing capacity without requiring higher lateral density, thereby maintaining adequate spacing between conductive features and minimizing contact resistance.
Data Source
AI summary
An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first dielectric layer disposed over a substrate, a second dielectric layer disposed over the first dielectric layer, and a first conductive feature disposed in the second dielectric layer. The first conductive feature has a first top critical dimension and a first height. The structure further includes a second conductive feature disposed in the first and second dielectric layers. The second conductive feature has a second top critical dimension substantially greater than the first top critical dimension and a second height substantially greater than the first height.