Multilayer Interdigital Capacitor Structure for Higher Capacitance
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Solution Overview
Problem
Existing interdigital capacitors (IDCs) have limitations in capacitance and impedance due to their single-layer structure and circular or low-aspect-ratio via layers, which restricts their performance in electronic devices.
Innovation Solution
The development of a routable lead frame (RLF) substrate with multi-layer interdigital capacitors that include any-shape via layers and an elevated trace, allowing for enhanced capacitive coupling and increased capacitance, fabricated using a process that builds up layers with any-shape vias and eliminates the need for circular or low-aspect-ratio vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If single-layer interdigital capacitor structure is used, then manufacturing process is simple, but capacitance is limited and impedance performance is insufficient
Solution Approach 1:
The patent transitions from a single-layer planar structure to a multi-layer three-dimensional structure. The interdigital capacitor is formed across multiple layers with conductive traces on different levels, allowing capacitance to be generated not only in the planar direction but also in the vertical dimension. This dimensional expansion significantly increases the effective capacitance area without proportionally increasing the footprint area.
Solution Approach 2:
The patent implements a nested structure where multiple conductive layers are stacked vertically with dielectric materials between them. Each layer contains interdigital fingers that interlock with corresponding fingers on adjacent layers, creating a nested configuration similar to dolls within dolls. This nesting approach maximizes the use of vertical space to increase capacitance density.
2Reliability
If circular or low-aspect-ratio via layers are used, then fabrication is easier, but capacitive coupling is restricted and capacitance is limited
Solution Approach 1:
The patent replaces traditional circular via holes with elongated via structures that have high aspect ratios and non-circular geometries. These asymmetric via shapes are specifically designed to maximize the conductive coupling area between layers while maintaining manufacturability through controlled deposition processes. The elongated shape provides greater surface area for capacitive coupling compared to circular vias of similar footprint.
Solution Approach 2:
The patent changes the geometric parameters of the via structures from circular to elongated shapes with controlled aspect ratios. By adjusting the length, width, and depth parameters of the via holes, the design optimizes the balance between capacitive coupling efficiency and fabrication ease. The via parameters are specifically tuned to achieve maximum capacitance while remaining compatible with standard semiconductor manufacturing processes.
3Reliability
If multi-layer routable lead frame substrate is used, then capacitance and impedance performance improve, but manufacturing complexity increases
Solution Approach 1:
The patent divides the lead frame substrate into multiple discrete layers, each performing specific functions. The conductive traces, dielectric materials, and via structures are segmented into separate layers that can be independently designed, fabricated, and assembled. This segmentation allows for modular manufacturing where each layer can be optimized separately, reducing the overall manufacturing complexity despite the increased number of layers.
Solution Approach 2:
The multi-layer routable lead frame substrate serves multiple functions simultaneously: it provides mechanical support, electrical interconnection, capacitive coupling, and thermal management. The same substrate structure that enables high-performance interdigital capacitors also serves as the package substrate for mounting semiconductor devices, eliminating the need for separate capacitor components and reducing overall system complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The RLF substrate IDCs demonstrate higher capacitance, lower impedance, and improved capacitive performance compared to single-layer IDCs, enabling better impedance matching and filtering in electronic devices without increasing design or fabrication costs.
Implementation Method 1
The first-side trace and the first-side conductive via are capacitively coupled to the second-side trace and the second-side conductive via through the dielectric molding material
Implementation Method 2
dielectric molding material disposed between the interdigitated fingers of the conductive layer and between the first-side conductive via and the second-side conductive via
Data Source
AI summary
A routable lead frame (RLF) substrate has a conductive layer having first- and second-side traces having first fingers and second fingers, respectively, which are interdigitated with each other. A via layer is over the conductive layer. A first-side conductive via of the via layer is conductively coupled to the first-side trace. A second-side conductive via of the via layer is conductively coupled to the second-side trace. Dielectric molding material is disposed between the interdigitated fingers of the conductive layer and between the first-side conductive via and the second-side conductive via. The fingers and vias form an interdigital capacitor (IDC) useful in impedance matching and filtering.