Multi-layer Inter-gate Dielectric Structure for Split-gate Memory
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Solution Overview
Problem
Split-gate semiconductor devices face issues with inter-gate dielectric structures that are weakened due to uneven etching during fabrication, leading to excessive leakage current and potential dielectric breakdown, as gaps are filled with lower quality dielectrics or voids form.
Innovation Solution
A method involving the formation of a dielectric structure with alternating layers of two or more dielectric films, each with a width of 30 Å or less, over a gate stack, which are selectively etched to create inter-gate dielectric structures, providing robust electrical isolation and resistance to wet etch stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-layer inter-gate dielectric structure is used, then the manufacturing process is simple, but the electrical isolation is weak and leakage current increases
Solution Approach 1:
The patent applies composite materials by using multiple dielectric layers (e.g., silicon dioxide and silicon nitride) with different properties. Each layer contributes different characteristics: silicon dioxide provides good electrical isolation, while silicon nitride offers etch resistance. This composite structure resolves the contradiction by achieving both strong electrical isolation and manufacturing feasibility through the synergistic combination of materials.
Solution Approach 2:
The patent segments the single-layer dielectric structure into multiple thin layers. By dividing the inter-gate dielectric into several layers with different compositions and thicknesses (e.g., 50-200 nm each), the structure achieves superior electrical isolation while maintaining manufacturability. Each layer can be optimized for specific functions, resolving the trade-off between simplicity and reliability.
2Productivity
If wet etch stages are used to remove dielectric films, then the fabrication process is effective, but uneven etching occurs causing gaps and voids
Solution Approach 1:
The patent applies local quality by creating a multi-layer structure where each layer has different etch resistance properties. The alternating layers of silicon dioxide and silicon nitride ensure that no single layer is completely removed during wet etching, as the etchant selectively removes one material while leaving the other intact. This local variation in etch resistance prevents the formation of gaps and voids, resolving the contradiction between fabrication effectiveness and etch uniformity.
Solution Approach 2:
The patent uses beforehand cushioning by designing the multi-layer dielectric structure to anticipate and prevent the harmful effects of uneven etching. The alternating layers act as a buffer system where, if one layer is over-etched, the underlying layer provides protection and prevents complete removal, thus preventing gap formation before it can occur during the etching process.
3Productivity
If the inter-gate dielectric structure is made thinner, then the device density increases, but the dielectric breakdown voltage decreases
Solution Approach 1:
The patent uses composite materials to achieve both thin overall thickness (for high device density) and high breakdown voltage. By combining multiple dielectric layers with different breakdown characteristics, the structure achieves superior overall breakdown strength compared to a single layer of equivalent total thickness. The alternating layers of silicon dioxide and silicon nitride provide cumulative breakdown resistance while maintaining a thin profile.
Solution Approach 2:
The patent segments the dielectric thickness into multiple thin layers, each contributing to the overall breakdown voltage. Instead of one thick layer, the structure uses several thinner layers (e.g., 50-200 nm each) that collectively provide higher breakdown strength. This segmentation allows the device to achieve high density through reduced total thickness while maintaining or even improving breakdown voltage through the multiplicative effect of multiple interfaces and material properties.
Data Source
AI summary
A memory device that has a first gate disposed adjacent to a second gate and a first dielectric structure disposed between the first and second gates. The first dielectric structure has at least four layers of oxide and nitride films arranged in an alternating layer, in which each of the at least four or more layers includes a width in an approximate range of 30 Å or less. The first dielectric structure further includes a top surface that is substantially un-etched.