Multi-Layer Mask Pattern for Semiconductor Etching
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in forming high-density patterns with ultra-fine widths and intervals due to limitations in photolithography resolution, leading to leaning defects and etching defects in mask patterns, which affect the quality and integrity of the final semiconductor device patterns.
Innovation Solution
A method involving the formation of a mask pattern with multiple layers of varying densities, where a high-density lower masking layer and a low-density upper masking layer are used, along with spacers to etch the etch target layer, allowing for the reduction of leaning defects and ensuring the survival of spacers as etching masks, thereby preventing etching defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single low-density mask pattern is used, then the photolithography process can be simplified, but leaning defects occur in the mask pattern
Solution Approach 1:
The mask pattern is divided into multiple layers with different densities. The lower masking layer has a first density and the upper masking layer has a second density that is less than the first density. This segmentation allows each layer to perform its specific function: the lower dense layer provides structural support to prevent leaning, while the upper less dense layer allows for proper photolithography patterning.
Solution Approach 2:
Different regions of the mask pattern have different densities optimized for their local functions. The lower layer near the substrate has higher density for mechanical stability, while the upper layer has lower density for photolithography compatibility. This local quality variation resolves the contradiction between structural integrity and patterning ease.
2Manufacturing precision
If the mask pattern is made thinner to reduce defects, then the leaning defects may be reduced, but the spacers cannot survive as etching masks
Solution Approach 1:
The mask pattern thickness is segmented into multiple layers, allowing the total thickness to be sufficient for spacer survival while maintaining a thin effective patterning thickness. The lower dense layer provides the necessary mechanical strength and thickness support, while the upper less dense layer maintains the thin profile needed for high-quality patterning.
Solution Approach 2:
The mask pattern uses a composite structure of two materials with different densities. The lower layer material provides mechanical strength and thickness, while the upper layer material provides photolithography compatibility. This composite approach allows the mask to simultaneously satisfy both the thickness requirement for spacer survival and the thinness requirement for defect reduction.
3Productivity
If ultra-fine patterns are formed beyond photolithography resolution limit, then higher integration density is achieved, but the patterns cannot be reliably formed
Solution Approach 1:
The patterning process is segmented into multiple steps using the multi-layer mask. The lower dense layer provides a stable foundation that maintains pattern fidelity, while the upper less dense layer allows for precise photolithography formation of ultra-fine features. This segmentation enables reliable formation of patterns at dimensions approaching or below the conventional photolithography resolution limit.
Solution Approach 2:
The density parameter of the mask pattern is changed by using multiple layers with different densities. This parameter change allows the mask to optimize both mechanical stability and photolithography performance, enabling reliable formation of ultra-fine patterns that would otherwise be beyond the resolution limit of standard photolithography processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor device patterns with reduced leaning and etching defects, ensuring the precision and quality of ultra-fine patterns within the resolution limits of existing photolithography processes, enhancing the efficiency and cost-effectiveness of semiconductor device fabrication.
Implementation Method 1
the forming of the mask pattern may include forming the lower masking layer at a process temperature equal to or higher than room temperature and smaller than or equal to about 400° C. using an atomic layer deposition (ALD) process
Implementation Method 2
the forming of the mask pattern may include forming the upper masking layer using a chemical vapour deposition (CVD) process
Implementation Method 3
the first etching operation may include dry etching the upper masking layer
Implementation Method 4
the second etching operation may include wet etching the lower masking layer
Data Source
AI summary
Methods of forming patterns for semiconductor devices are provided. A method may include preparing a substrate including an etch target layer on a surface of the substrate; forming a mask pattern that includes a lower masking layer having a first density and an upper masking layer having a second density that is less than the first density, on the etch target layer; forming spacers that cover sidewalls of the lower masking layer and the upper masking layer; removing the mask pattern; and etching the etch target layer by using the spacers as an etching mask.