Multilayer Masking for Precise Nano-FET Epitaxial Formation
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Solution Overview
Problem
As the semiconductor industry continues to reduce minimum feature sizes, challenges arise in the manufacturing of nano-FETs, including the need for efficient formation of epitaxial source/drain regions and gate structures while maintaining process efficiency and ease of mask layer removal.
Innovation Solution
The method involves forming stacks of semiconductor layers, etching to create epitaxial source/drain regions, and forming gate structures over these layers, with specific masking and treatment processes to improve efficiency and ease of removal, applicable to nano-FETs, FinFETs, and planar transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to improve integration density, then more components can be integrated into a given area, but manufacturing challenges and process complexity increase
Solution Approach 1:
The mask layer is divided into multiple segments (first mask layer and second mask layer) with different materials and functions. The first mask layer (silicon nitride) provides primary patterning protection, while the second mask layer (silicon oxide) provides additional protection and facilitates selective removal. This segmentation allows each layer to be optimized for specific process requirements, enabling reduced feature sizes while maintaining manufacturability.
Solution Approach 2:
Different regions of the mask structure have different material compositions tailored to local process needs. The first mask layer uses silicon nitride in regions requiring high etch resistance, while the second mask layer uses silicon oxide in regions where selective removal is needed. This local differentiation of material properties enables precise control over the manufacturing process at reduced feature sizes.
2Manufacturing precision
If epitaxial source/drain regions are formed with precise masking to improve manufacturing precision, then feature accuracy improves, but mask layer removal becomes more difficult
Solution Approach 1:
The mask layer structure changes its material composition and physical properties at different stages of the process. The dual-layer structure (silicon nitride + silicon oxide) allows the mask to maintain high precision during epitaxial growth, then undergoes parameter changes during selective removal where the silicon oxide layer can be selectively etched away while the silicon nitride layer remains intact for continued protection.
Solution Approach 2:
The second mask layer (silicon oxide) acts as an intermediary between the first mask layer (silicon nitride) and the epitaxial source/drain regions. It provides the necessary protection during precise feature formation, then facilitates easy removal through selective etching processes, mediating between the need for precision and the need for ease of removal.
3Manufacturing precision
If multiple masking layers are used to improve manufacturing precision, then feature formation accuracy improves, but process steps increase
Solution Approach 1:
The dual-layer mask structure performs multiple functions simultaneously: the first mask layer (silicon nitride) provides primary patterning and etch protection, while the second mask layer (silicon oxide) provides additional protection and enables selective removal. This multi-functionality allows the mask system to achieve high precision feature formation without requiring separate masking steps for each function, thereby maintaining process efficiency.
Solution Approach 2:
The first and second mask layers are combined into a single integrated masking system that is formed and processed together. Rather than applying separate masks at different stages, both layers are deposited and patterned in an integrated sequence, merging multiple protective functions into a unified structure that simplifies the overall process flow while maintaining high precision.
Data Source
AI summary
A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.