Multi-Layer Memory In-Service Software Updating
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Solution Overview
Problem
Existing methods for updating software in peripheral devices, such as network adapters and storage devices, face challenges in minimizing downtime during the update process, especially when updating critical bus-maintenance software.
Innovation Solution
The solution involves a peripheral device with multiple processors, where a first processor manages communication over a peripheral bus by executing bus-maintenance software from a multi-layer memory, and a second processor updates the software by loading the updated version into higher hierarchy memory layers and invalidating the existing version, forcing the first processor to fetch and execute the updated version.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If software update is performed by replacing existing version directly, then update speed is improved, but system downtime increases and reliability decreases
Solution Approach 1:
The software update process is segmented into multiple stages: loading updated version to higher memory layer, validating readiness, atomic swap via invalidation, and execution resumption. This segmentation allows the update operation to be broken down into discrete, manageable phases that can proceed in parallel with normal operation, reducing both downtime and update time.
Solution Approach 2:
The updated software version is loaded to the higher memory layer (L3 cache or system memory) and validated before the actual execution switch. This preliminary action allows the update to be prepared in advance without blocking the running process, enabling a smooth transition when the swap occurs.
2Loss of time
If multi-layer memory hierarchy is used for software storage, then update downtime is reduced, but device complexity increases
Solution Approach 1:
The existing multi-layer memory hierarchy (L1 cache, L2 cache, L3 cache, system memory) is leveraged for software storage and update purposes. Instead of adding dedicated update memory structures, the patent utilizes the universal memory hierarchy already present in the system, performing multiple functions (execution, caching, updating) through the same infrastructure.
Solution Approach 2:
The higher memory layer (L3 cache or system memory) acts as an intermediary between the running software version in lower cache layers and the updated version being loaded. This intermediary layer provides a buffer that allows the update to be staged separately from the execution environment, enabling atomic swaps without direct complexity in the execution path.
3Reliability
If atomic invalidation is used to switch software versions, then update reliability is improved, but execution time during transition increases
Solution Approach 1:
The updated software version is copied to the higher memory layer before the atomic invalidation occurs. This copying operation allows the new version to be prepared in parallel with the running process, and when the invalidation happens, the copy is already ready for immediate execution, minimizing transition time while ensuring reliability.
Data Source
AI summary
A peripheral device includes a bus interface, a first processor and a second processor. The bus interface is to communicate over a peripheral bus. The first processor is to manage communication over the peripheral bus by executing bus-maintenance software code, the bus-maintenance software code being executed from one or more first layers of a multi-layer memory. The second processor is to update the bus-maintenance software code from an existing version to an updated version, by (i) loading the updated version to one or more second layers of the multi-layer memory, higher in hierarchy than the or one more first layers, and (ii) invalidating the existing version in the one or more first layers, thereby forcing fetching of the updated version from the one or more second layers to the one or more first layers and to start executing the updated version.