Multilayer Microfluidic Chip Fabrication Without Wafer Bonding

The patent removes the wafer bonding step from the manufacturing process entirely. Instead of bonding separate wafers together to form multilayer channels, the invention uses a single wafer with sacrificial layers that are selectively removed to create the multilayer channel structure, eliminating the need for bonding and associated costs.

The sacrificial layers (spin-on carbon and inorganic dielectric materials) are deposited and patterned in advance during the fabrication process. These preliminary structures guide the subsequent self-aligned etching steps, allowing the multilayer channel geometry to be defined before any channel formation occurs, thereby eliminating the need for bonding to achieve structural integrity.

The bonding step is extracted from the process, eliminating the source of yield loss from insufficient bonding and pillar damage during bonding. The single-wafer approach with sacrificial layers inherently prevents these bonding-related failures.

The pillar structures and channel geometries are defined in advance using self-aligned lithography and etching on a single wafer. This preliminary definition of all channel structures eliminates the risk of pillar damage that occurs during subsequent bonding operations, thereby improving manufacturing yield.

The patent transitions from increasing pillar height in one dimension to stacking multiple horizontal channel layers in the vertical dimension. This allows the system to achieve higher volumetric flow rates by adding parallel flow paths through self-aligned multilayer structures rather than relying on taller, less stable pillars.

The flow path is segmented into multiple horizontal layers stacked vertically. Each layer contains complete inlet/outlet openings and pillar arrays that function independently but collectively provide enhanced volumetric flow capacity. This segmentation allows maintaining stable, manufacturable pillar heights while achieving high flow rates through parallel channels.

The patent merges multiple lithography and etching operations into self-aligned processes. The sacrificial layers and channel structures are defined using self-aligned lithography where previously separate alignment steps are combined, reducing the total number of lithography steps while maintaining precise pillar array definition through the self-alignment mechanism.

The sacrificial layers (spin-on carbon and inorganic dielectric materials) serve as intermediary structures that enable self-aligned patterning. These intermediaries are deposited and patterned to define the channel geometries and pillar locations, allowing subsequent etching steps to automatically align with previously defined features without requiring additional lithography alignment steps.