Multilayer Nanosheet FET Structure for Threshold Voltage Control
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Solution Overview
Problem
As IC devices shrink, there is a need to increase integration density and achieve high operating speed and accuracy, particularly in horizontal nanosheet FETs, where existing structures fail to precisely control threshold voltage effectively.
Innovation Solution
The IC device incorporates a fin-type active region with a multilayered nanosheet structure, including a first outer semiconductor sheet, a core semiconductor sheet, and a second outer semiconductor sheet, stacked vertically, surrounded by a gate line, and contacted by source/drain regions, allowing for precise control of threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of IC devices is reduced to increase integration density, then the number of FETs per substrate area increases, but the operating speed and accuracy of individual FETs deteriorate
Solution Approach 1:
The patent transitions from planar FET structures to vertically stacked nanosheet FETs, utilizing the vertical dimension to increase integration density while maintaining individual device performance. Multiple nanosheets are stacked vertically above a common fin structure, allowing more channels per footprint area without compromising the electrical characteristics of each channel.
Solution Approach 2:
The channel region is segmented into multiple discrete nanosheets stacked vertically, with each nanosheet forming an independent conduction path. This segmentation allows each nanosheet to be precisely controlled by the gate, maintaining high operating accuracy while increasing the total number of channels within the same substrate area.
2Quantity of substance
If conventional FET structures are used to achieve high integration density, then device size is reduced, but threshold voltage control precision deteriorates
Solution Approach 1:
Each nanosheet is formed with specific local material compositions and doping characteristics that can be independently optimized. The gate structure provides localized control over each nanosheet's threshold voltage, allowing precise adjustment of electrical characteristics for each channel while maintaining high integration density through vertical stacking.
Data Source
AI summary
An integrated circuit device includes a fin-type active region on a substrate, a nanosheet on a fin top surface of the fin-type active region, the nanosheet being apart from the fin top surface of the fin-type active region in a vertical direction, a gate line surrounding the nanosheet on the fin-type active region, and a source/drain region on the fin-type active region, the source/drain region being in contact with the nanosheet, wherein the nanosheet includes a multilayered sheet comprising a first outer semiconductor sheet, a core semiconductor sheet, and a second outer semiconductor sheet, which are sequentially stacked in the vertical direction.