Multi-layer Non-volatile Memory Device with Common Bit Plane
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current non-volatile memory devices face challenges in increasing operational speed and integration capacity as semiconductor products become smaller and require enhanced data processing capabilities, necessitating a more efficient multi-layer structure for data storage.
Innovation Solution
A non-volatile memory device is designed with a multi-layer structure comprising variable resistors, common bit planes, bit lines, and cell selection transistors, where variable resistors are arranged in a matrix form and coupled with switching devices, allowing for data storage and access through a layered architecture that includes layer selection transistors and decoder lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single-layer structure is used for non-volatile memory, then the device structure is simple, but the integration capacity and data storage capability are limited
Solution Approach 1:
The patent transitions from a single-layer structure to a multi-layer structure by adding the common bit plane as an additional dimensional layer. Variable resistors in different layers are coupled to the same common bit plane, enabling three-dimensional stacking that increases storage capacity without proportionally increasing planar footprint, thus resolving the contradiction between storage capacity and structural complexity.
Solution Approach 2:
The common bit plane serves multiple functions: it acts as a shared electrode for variable resistors across multiple layers, provides a common reference potential, and enables selective access to different layers through the switching devices. This multi-functionality increases storage capacity while avoiding proportional increases in overall device complexity.
2Quantity of substance
If more layers are added to increase integration capacity, then data storage capability increases, but wiring resistance and access complexity increase
Solution Approach 1:
Multiple layers of variable resistors are merged through their common coupling to shared bit planes. This merging approach allows vertical stacking of storage elements while sharing common conductive paths, increasing integration capacity without proportionally increasing the total length and resistance of wiring compared to fully distributed multi-layer architectures.
3Quantity of substance
If variable resistors are arranged in matrix form with multiple layers, then data storage capacity increases, but the complexity of selecting and accessing specific cells increases
Solution Approach 1:
Switching devices are introduced as intermediary elements between the bit lines and variable resistors, and between layer selection lines and common bit planes. These intermediaries enable selective activation of specific memory cells through coordinated control signals, simplifying the access mechanism for multi-layer matrix arrangements while maintaining high storage capacity.
Solution Approach 2:
The memory array is segmented into multiple independently selectable layers through the layer selection transistors and layer selection lines. Each layer can be selectively accessed or deactivated, allowing the system to manage complex multi-layer matrices by dividing them into manageable segments that can be operated independently, thus reducing access complexity.
Data Source
AI summary
Provided is a non-volatile memory device that may include a plurality of variable resistors, each of the variable resistors having first and second terminals, the plurality of variable resistors arranged as a first layer of a plurality of layers and having data storage capability, at least one common bit plane arranged as a second layer of the plurality of layers and coupled to the first terminal of each of the variable resistors of the first layer, and a plurality of bit lines coupled to the second terminal of each of the variable resistors of the first layer.