Multilayer Override Circuit for Unpredictable Silicon Bring-Up
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Solution Overview
Problem
Conventional semiconductor debugging methods face challenges with unpredictable silicon behavior, leading to costly device recalls, re-spins, and delays due to hard configurations that are not reversible, requiring full tape-outs for validation, and lack flexibility in handling silicon uncertainties.
Innovation Solution
A multilayered override system with hardware, software, and fixed metal plug configurations that intercept and override values between provider and consumer blocks, allowing for flexible and reversible fallback options to ensure device functionality during silicon bring-up, enabling diagnostic software to identify and correct issues without full tape-outs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hard configurations (metal plugs) are used for fallback logic, then device functionality is ensured during silicon bring-up, but the configurations are not reversible and require full tape-outs for any changes
Solution Approach 1:
The patent implements dynamic override circuits that can switch between original circuit behavior and fallback logic based on runtime conditions. The override circuits include control logic that activates fallback paths when unpredictable silicon behavior is detected, allowing the system to adapt its configuration dynamically rather than being fixed at tape-out. This resolves the contradiction by making the configuration flexible while maintaining reliability through automatic fallback activation.
Solution Approach 2:
The patent introduces intermediate override circuits as mediators between the original circuit logic and the fallback logic. These override circuits include multiplexers and control logic that can selectively route signals through either the original path or the fallback path. This intermediary layer provides configurability without requiring full tape-outs, as the override circuits can be programmed or configured after fabrication to select appropriate fallback behaviors.
2Reliability
If full validation cycle is performed before tape-out, then silicon uncertainties are identified, but development time and cost increase substantially
Solution Approach 1:
The patent implements preliminary override circuits and fallback logic during the design phase that can be activated later during silicon bring-up. Instead of performing complete validation before tape-out, the system prepares override paths in advance that can be activated if silicon uncertainties are detected. This allows faster initial tape-out while maintaining the ability to verify and correct issues through controlled activation of fallback logic, reducing overall development time while preserving verification capability.
Solution Approach 2:
The patent incorporates fallback logic and override circuits as a cushion against unpredictable silicon behavior before actual problems occur. These pre-prepared fallback paths include alternative logic implementations and override mechanisms that can be activated when silicon issues are detected during bring-up. This beforehand cushioning allows the system to handle silicon uncertainties without requiring complete re-validation cycles, thus reducing development time while maintaining reliability.
3Adaptability or versatility
If multiple hard configurations are implemented, then comprehensive fallback options are available, but selection and validation of specific configurations requires subsequent tape-outs
Solution Approach 1:
The patent implements universal override circuits that can handle multiple fallback scenarios through a single configurable infrastructure. The override circuits include multiplexers and control logic that can be programmed to select from multiple fallback options without requiring separate hardwired paths for each scenario. This multi-functional approach provides comprehensive fallback options while simplifying configuration management, as the same override circuit infrastructure can be configured for different scenarios through programming rather than requiring separate tape-outs for each configuration.
Data Source
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AI summary
An override circuit (200) for a semiconductor chip including an override interface (210), a timer (214), and a priority override controller (212). The override interface is configured to select between an original value (ORG) and a selected override value (SOVR) for providing an output value (OUT). The timer provides a timeout signal (TO) after a predetermined time period after start-up. The priority override controller has a default configuration for controlling the override interface to select the original value as the output value at start-up until the timeout signal is provided, and then to control the override interface to select a fixed metal hardware override value as the selected override value. The priority override controller is configurable to control the override interface to instead select at least one configurable override value as the selected override value upon start-up. The configurable override value may be a software value for diagnostic purposes, or a hardware fuse value as a final value.