3D Multilayer Semiconductor with Oxide-to-Oxide Bonding
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Solution Overview
Problem
Wires in integrated circuits (ICs) dominate performance, functionality, and power consumption as they degrade with scaling, while existing 3D stacking techniques for semiconductor devices face challenges in achieving low construction costs and optimal device performance due to the use of poly-silicon for active memory cell channels.
Innovation Solution
The development of multilayer semiconductor devices with monocrystalline channels, utilizing epitaxial growth and oxide-to-oxide bonding to form self-aligned transistors across multiple levels, reducing the need for successive layer transfers and sharing lithography steps, thereby enhancing device performance and lowering construction costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 3D stacking techniques are used to reduce wire lengths and improve transistor density, then device performance and functionality are improved, but construction costs increase due to the use of poly-silicon for active memory cell channels and the need for successive layer transfers
Solution Approach 1:
The patent changes the material parameter from poly-silicon to monocrystalline silicon for the channel region, and changes the fabrication parameter from successive layer transfers to a single lithography step with epitaxial growth. This resolves the contradiction by achieving both high transistor density through 3D stacking and reduced construction costs through simpler manufacturing processes and superior material properties that enable lower processing temperatures and fewer fabrication steps.
Solution Approach 2:
The patent employs composite material structures including monocrystalline silicon channels, epitaxial silicon layers, and selective silicon removal to create the 3D stacked configuration. This composite approach allows the device to achieve both high density through vertical stacking and cost efficiency through the use of standard silicon-based materials that can be processed with existing fabrication techniques.
2Ease of manufacture
If poly-silicon is used for active memory cell channels in 3D stacking, then construction costs are reduced, but device performance deteriorates due to higher cell to cell performance variations and lower drive
Solution Approach 1:
The patent changes the material parameter from poly-silicon to monocrystalline silicon for the channel region. Monocrystalline silicon provides superior electrical properties with lower defect density and more uniform carrier mobility, directly resolving the contradiction by achieving both cost-effectiveness through standard fabrication processes and high reliability through reduced cell-to-cell performance variation and improved drive current.
3Reliability
If successive layer transfers are used to construct 3D stacked devices, then device performance is improved, but manufacturing complexity increases and construction costs rise
Solution Approach 1:
The patent merges multiple fabrication steps into a single lithography step. Instead of transferring layers sequentially, the invention forms all memory cell structures for multiple stacked levels in one lithography exposure, followed by selective epitaxial growth and silicon removal. This merging dramatically reduces manufacturing process complexity while maintaining the performance benefits of 3D stacking through precise self-alignment of the monocrystalline channels.
Solution Approach 2:
The patent performs preliminary epitaxial growth of monocrystalline silicon layers before selective removal to form the 3D stacked structure. This preliminary action of growing high-quality monocrystalline material throughout the stack enables subsequent selective etching to create the vertical channels, achieving complex 3D architecture from a simpler preliminary 2D epitaxial structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in lower construction costs and improved device performance by aligning transistors across layers with atomic precision, reducing wire lengths and maintaining low wiring delay, thus overcoming the limitations of traditional 3D stacking methods.
Implementation Method 1
utilizing epitaxial growth and oxide-to-oxide bonding to form self-aligned transistors across multiple levels
Implementation Method 2
utilizing epitaxial growth and oxide-to-oxide bonding to form self-aligned transistors across multiple levels
Data Source
AI summary
A method of making a 3D multilayer semiconductor device, including: providing a first substrate including a first level, the first level including a first single crystal silicon layer; providing a second substrate including a second level, the second level including a second single crystal silicon layer; performing an epitaxial growth of a SiGe layer on top of the second single crystal silicon layer; performing an epitaxial growth of a third single crystal silicon layer on top of the SiGe layer, the third silicon layer has an average thickness of less than 2,000 nm; forming a plurality of second transistors each including a single crystal channel; forming many metal layers interconnecting the plurality of second transistors; and then performing a bonding of the second level onto the first level, where performing the bonding includes making oxide-to-oxide bond zones; and performing removal of a majority of the second single crystal silicon layer.