Multilayer Initial Oxide for BST Capacitor Thermal Mismatch
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Solution Overview
Problem
Ferroelectric capacitors on silicon substrates face challenges due to thermal expansion coefficient mismatch between the silicon substrate and the BST dielectric layers, leading to delamination and cracking issues, which affect the reliability and performance of the devices.
Innovation Solution
A method involving the formation of a multilayer initial oxide with a higher thermal expansion coefficient by depositing and annealing silicon dioxide layers with a modifier layer, creating amorphous polysilicates that reduce stress and prevent delamination, while maintaining the smoothness and adhesion of the SiO2 layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard SiO2 initial oxide layer is used on silicon substrate, then the TEC mismatch with BST dielectric is extremely high, but this leads to delamination and cracking of the device stack
Solution Approach 1:
The patent applies composite materials by creating a multilayer initial oxide structure consisting of SiO2 layers combined with a modifier layer containing alkali or alkaline earth metals. This composite structure has an effective TEC that is higher than pure SiO2 (0.5 ppm/K) and can be tuned to better match the BST dielectric TEC (5.0-8.8 ppm/K), thereby reducing thermal expansion mismatch stress and preventing delamination while maintaining stack integrity
Solution Approach 2:
The patent changes the TEC parameter of the initial oxide layer by incorporating alkali or alkaline earth metals into the SiO2 matrix. The modifier layer is annealed to form amorphous polysilicates with higher TEC values. By adjusting the composition and thickness of the modifier layer, the effective TEC of the initial oxide can be tuned to optimize the match with BST, reducing thermal stress without compromising device reliability
2Object-affected harmful factors
If the TEC of the initial oxide is increased to match BST, then thermal stress is reduced, but the smoothness and adhesion properties of SiO2 may be compromised
Solution Approach 1:
The patent applies local quality by creating a multilayer structure where different layers have different functions: the SiO2 layers provide smoothness and adhesion strength, while the modifier layer provides higher TEC to reduce thermal mismatch. Each layer is optimized for its specific function, and the combination achieves both adhesion strength and thermal compatibility that neither material could provide alone
Solution Approach 2:
The modifier layer acts as an intermediary between the silicon substrate and the BST dielectric. It has higher TEC than SiO2 to reduce thermal mismatch stress, while the SiO2 layers maintain the smooth interface and strong adhesion properties. The intermediary layer transfers and distributes thermal stress, protecting the adhesion interface from cracking while preserving the beneficial properties of SiO2
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the RF performance and reliability of tunable capacitors by reducing thermal expansion mismatch-induced stress, preventing delamination, and improving the mechanical strength of the SiO2 layer, thereby increasing the durability and efficiency of the capacitors.
Implementation Method 1
annealing the multilayer initial oxide resulting in an annealed multilayer initial oxide, wherein the annealing causes the alkali or alkali earth metals to chemically react at the interfaces between the modifier layer and the SiO2
Implementation Method 2
the annealing causes the alkali or alkali earth metals to chemically react at the interfaces between the modifier layer and the SiO2 to form alkali or alkali earth silicates
Implementation Method 3
compensating for a Thermal Expansion Coefficient mismatch for a silicon substrate of a device
Data Source
Figure 1A
Figure 1b
Figure 2A~2C
AI summary
A device that incorporates teachings of the subject disclosure may include, for example, a multilayer initial oxide on a silicon substrate, where the multilayer initial oxide comprises amorphous polysilicates and a group one metal or a group two metal; a first electrode layer on the multilayer initial oxide; a dielectric layer on the first electrode layer; a second electrode layer on the dielectric layer, where an edge alignment spacing between at least one pair of corresponding electrode edges of two electrode layers of the capacitor is two microns or less; and connections for the first and second electrode layers. Other embodiments are disclosed.