Multi-Layer Package Routing Lines for High-Density IC Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current IC packaging technologies face limitations in achieving high interconnect density and data transmission frequencies, particularly for next-generation multi-chip packaging, as they are constrained by lower line metallization densities and data transmission frequencies, which are insufficient for evolving bandwidth-intensive applications.
Innovation Solution
The development of semi-additive processing (SAP) techniques for fabricating IC packages with multi-layered metallization features, including the use of distinct metal layers and advanced etching processes to reduce dimensional loss and surface roughness, enabling higher line densities and improved signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single-layer metallization is used, then manufacturing process is simpler, but interconnect density and signal integrity deteriorate
Solution Approach 1:
The metallization line is divided into multiple layers (first metallization layer and second metallization layer) with different materials. The first layer uses a first metal (e.g., Pd, Ru, Pt, Ti, or Au) and the second layer uses a second metal (e.g., Cu, Al, or Ag), allowing each layer to be optimized for specific functions such as adhesion, conductivity, and density, thereby achieving higher interconnect density while maintaining manufacturing feasibility through specialized processes for each layer
Solution Approach 2:
The patent employs composite metallization structures where different metal materials are combined in layered configurations. This composite approach allows the integration of materials with complementary properties (e.g., barrier properties, electrical conductivity, mechanical strength) to achieve superior interconnect density and signal integrity that cannot be obtained with single-material metallization
2Productivity
If higher line density is achieved, then bandwidth increases, but signal insertion loss increases
Solution Approach 1:
The patent changes material parameters by selecting specific metals for each layer (first metal from Pd, Ru, Pt, Ti, or Au; second metal from Cu, Al, or Ag) and optimizing their thicknesses (first thickness of at least 100 nm, second thickness greater than first thickness). These parameter changes reduce signal insertion loss while enabling higher line density, thereby increasing bandwidth without proportionally increasing energy loss
Solution Approach 2:
The patent transitions from single-layer to multi-layer metallization architecture, adding the vertical dimension to the metallization structure. This dimensional change allows signal transmission paths to be distributed across multiple layers, reducing congestion and insertion loss in high-density interconnect configurations while maintaining manufacturing control
3Reliability
If multi-layer metallization is implemented, then signal integrity improves, but manufacturing process complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct stages for depositing and patterning the first metallization layer and the second metallization layer separately. This segmentation allows each layer to be processed with optimized techniques (e.g., sputtering for the first layer, electroplating for the second layer), improving signal integrity through better material properties while managing process complexity through modular manufacturing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased interconnect density and reduced signal insertion loss, supporting higher frequency data transmission and enhancing the performance of 2D, 2.5D, and 3D multi-chip packages by minimizing misalignment and maintaining signal integrity.
Implementation Method 1
a first metallization material layer is deposited over the dielectric material
Implementation Method 2
a second metallization material layer is plated onto a first portion of the first metallization material layer
Implementation Method 3
portions of the first metallization material layer are removed with an etch process that is selective to the first metallization material
Data Source
AI summary
IC die package routing structures including a bulk layer of a first metal composition on an underlying layer of a second metal composition. The lower layer may be sputter deposited to a thickness sufficient to support plating of the bulk layer upon a first portion of the lower layer. Following the plating process, a second portion of the lower layer may be removed selectively to the bulk layer. Multiple IC die may be attached to the package with the package routing structures responsible for the transmission of high-speed data signals between the multiple IC die. The package may be further assembled to a host component that conveys power to the IC die package.