Multi-Layer Passivation for Flat RDL Surfaces Above MIM Capacitors
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Solution Overview
Problem
The miniaturization of semiconductor devices leads to increased defects and stress concentration in interconnect structures, particularly in MIM capacitors, due to uneven top surfaces and thermal expansion differences, resulting in delamination and cracking, which affects production yield and reliability.
Innovation Solution
A multi-layer passivation structure is introduced, including a thicker second passivation layer with controlled thickness and planarization, followed by additional layers to smooth the surface, reducing stress and preventing cracking during manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device miniaturization is pursued to increase integration density, then productivity and integration capacity are improved, but manufacturing precision and reliability deteriorate due to increased defects and stress concentration
Solution Approach 1:
The passivation structure is divided into multiple layers (first passivation layer, second passivation layer, and optional third passivation layer) with different thicknesses and materials. This segmentation allows each layer to address specific stress and protection requirements, improving overall manufacturing precision and reliability while enabling continued device miniaturization
Solution Approach 2:
The patent modifies the passivation layer parameters by implementing a multi-layer structure where the second passivation layer has controlled thickness (at least 40% of the first passivation layer thickness) and specific material composition. This parameter change reduces stress concentration and prevents cracking, thereby improving manufacturing precision without sacrificing integration density
2Reliability
If passivation layer thickness is increased to reduce stress and prevent cracking, then reliability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
Rather than using a single thick passivation layer, the patent segments the passivation function into multiple layers with different thicknesses and materials. The second passivation layer provides stress relief while the first layer provides protection, achieving crack resistance without excessive overall complexity
Solution Approach 2:
The patent applies different material properties and thicknesses to different passivation layers based on local requirements. The second passivation layer has greater thickness specifically where stress concentration occurs, while other areas maintain appropriate thickness for protection, optimizing reliability without uniform complexity throughout
3Ease of manufacture
If uneven top surface is present to simplify manufacturing, then ease of manufacture is improved, but reliability deteriorates due to stress concentration and delamination
Solution Approach 1:
The patent addresses the surface unevenness issue by adding a vertical dimension solution - the second passivation layer is deposited to a controlled thickness that compensates for surface variations. This dimensional approach maintains ease of manufacture (no complex planarization needed) while preventing delamination through stress distribution
Data Source
AI summary
Disclosed semiconductor device manufacturing processes improve the flatness of a passivation layer deposited above a redistribution layer (RDL). When a thin passivation layer is deposited above the RDL, its top surface tends to become very uneven due to the large gaps that typically form over the etched portions of the RDL, particularly when the RDL is disposed over an underlying super high density metal-insulator-metal (MIM) capacitor. In order to reduce the incidence of stress concentration areas on the uneven surface, a thicker passivation layer is instead deposited to minimize gap formation therein, and a chemical mechanical planarization (CMP) process is then performed to further smooth the top surface thereof. Reduction of the stress in this manner reduces the incidence of cracking of the underlying MIM, which improves the overall pass rates of semiconductor devices so manufactured.