Multilayer Passive Circuit Topology for Compact RF Filters
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Solution Overview
Problem
Existing RF and IF filters in harsh environments require high-order, precision inductors and capacitors with low in-band loss and rapid roll-off, but current lumped element implementations are costly, labor-intensive, and bulky, especially for compact designs, due to the need for hand-tuning and large air-core inductors.
Innovation Solution
A multilayer passive circuit topology using embedded multilayer inductors and capacitors with parallel conductive traces and vias, allowing for high-Q, low-cost, and compact filter designs that reduce parasitics and enable tight tolerances, enabling efficient integration into printed wiring boards or surface mounting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If hand-tuned lumped element filters are used, then high Q and precision are achieved, but manufacturing complexity and cost increase exponentially
Solution Approach 1:
The filter is divided into multiple modular layers, each containing specific inductors and capacitors. This segmentation allows standardized manufacturing of individual layers that can be assembled through lamination, reducing overall assembly complexity while maintaining precision through controlled layer configurations
Solution Approach 2:
The invention changes the manufacturing parameters from manual hand-tuning to automated PCB fabrication processes. By controlling inductor and capacitor values through precise trace geometry and standard component selection during PCB manufacturing, the filter achieves required precision without exponential increases in assembly complexity
2Manufacturing precision
If air core solenoid inductors are used, then high Q is achieved, but component volume and package height increase
Solution Approach 1:
The invention transitions from three-dimensional air core solenoid inductors to planar inductors fabricated on PCB traces. By changing the inductor geometry from vertical solenoid to horizontal planar spiral, the design achieves comparable Q factors while dramatically reducing package height and overall volume
Solution Approach 2:
The invention uses PCB trace patterns that replicate the electrical characteristics of traditional air core inductors. Through careful design of trace geometry, width, and spacing, planar inductors on the PCB substrate copy the inductive behavior and Q factor performance of air core solenoids without requiring the bulky three-dimensional structure
3Volume of moving object
If surface mount components are used, then compact size is achieved, but precision and Q factor deteriorate
Solution Approach 1:
The invention merges the filter components directly into the PCB structure itself. Inductors are formed by PCB traces and capacitors are implemented as surface mount devices soldered to the PCB, eliminating the need for separate hand-tuned lumped element assemblies. This integration maintains compact size while achieving precision through controlled PCB manufacturing processes
Solution Approach 2:
The filter design performs preliminary optimization of inductor and capacitor values during the PCB design phase. By calculating and specifying exact trace dimensions, widths, and component values before manufacturing, the design achieves required precision without requiring post-assembly tuning, thus maintaining both compact size and manufacturing precision
4Volume of moving object
If tight packing density is used, then volume is reduced, but inductor interaction increases and performance decreases
Solution Approach 1:
The invention introduces ground planes and ground traces as intermediary elements between adjacent inductors on the PCB. These ground structures act as shields that electrically isolate neighboring inductors, preventing unwanted coupling and interaction while allowing tight packing density. The ground planes serve as mediators that maintain inductor isolation without increasing overall filter volume
Data Source
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AI summary
A multilayer passive circuit topology is disclosed. In one embodiment, a multilayer circuit is provided. The multilayer circuit comprises a multilayer inductor comprising a first set of parallel conductive traces formed on a first layer, a second set of parallel conductive traces formed on a second layer spaced apart from the first layer; and a plurality of vias that connect respective parallel conductive traces from the first and second layer to form inductor windings. The multilayer circuit further comprises a multilayer capacitor connected to an end of the inductor by a coupling via, the capacitor comprising a first conductive plate and a second conductive plate being spaced apart from one another and being formed on different layers.