Multilayer PCB Balun for Compact High-Power Class E Amplifiers
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Solution Overview
Problem
Push-pull class E amplifiers face limitations in generating high output power within a given physical size, especially at high output powers and low frequencies, due to excessive currents and low output impedance, which restricts the number of turns in the transformer, limiting power output.
Innovation Solution
The design incorporates a printed circuit board with additional line segments forming loops on multiple dielectric layers, allowing for a quarter wavelength configuration that includes a fourth line segment with weak coupling, enabling shorter first and second line segments and higher capacitance values, thereby increasing output power while maintaining a compact size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of turns in the transformer is increased to handle excessive currents, then the output power can be increased, but the physical size of the amplifier increases
Solution Approach 1:
The patent transitions from a planar single-layer layout to a three-dimensional multi-layer configuration. Line segments are distributed across multiple dielectric layers (first, second, and third layers) with vertical connections via vias, enabling the transformer to achieve higher effective turns density without increasing the horizontal footprint. This vertical stacking approach resolves the contradiction by adding the height dimension to accommodate more turns within the same base area.
Solution Approach 2:
The patent implements a nested structure where line segments from different layers are vertically aligned and electrically connected through vias, forming a compact multi-turn transformer. The inner layers are surrounded by outer layers, creating a nested configuration that maximizes the use of available space. This nesting allows multiple turns to be packed into a smaller volume, enabling higher output power without proportionally increasing the physical size.
2Power
If the capacitance values are increased to improve efficiency, then the output power generation is improved, but the device complexity increases
Solution Approach 1:
The patent combines multiple capacitance elements (first, second, third, and fourth capacitance values associated with different line segments and nodes) into an integrated matching network. These capacitances are strategically distributed across the multi-layer structure and work together as a unified system to achieve the desired impedance transformation and power output. By merging these capacitance elements into a coordinated network rather than treating them as separate components, the design achieves high output power while managing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for increased output power generation within the same physical size by enabling larger capacitance values and efficient current handling, reducing power consumption and improving efficiency.
Implementation Method 1
a first line segment arranged on the first dielectric layer... having a first end and a second end, the first end of the first line segment being coupled to the first output, a second line segment arranged on the first dielectric layer... the first end of the second line segment being coupled to the second output
Implementation Method 2
a quarter wavelength configuration that includes a fourth line segment with weak coupling, enabling shorter first and second line segments and higher capacitance values
Data Source
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AI summary
The present invention relates to a push-pull class E amplifier. Furthermore, the present invention relates to a device comprising such a push-pull amplifier. In the push-pull class E amplifier of the present invention a balun is realized using a multilayer printed circuit board, wherein the balanced terminals and connecting line segments are realized in an upper metal layer, whereas the unbalanced terminal and connecting line segments are realized in at least two lower metal layers.