Multilayer PCB Layout for Parasitic Inductance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional circuit board layouts for power converters face limitations in minimizing high frequency loop inductance, which affects efficiency and voltage overshoot, and are dependent on board thickness and shield layer requirements.
Innovation Solution
A multilayer circuit board layout design with a top layer, a bottom layer, and at least one inner layer connected by vias to form a high frequency power loop that minimizes parasitic inductance independently of board thickness without a shield layer, utilizing the first inner layer as a power loop return path for magnetic field self-cancellation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional lateral power loop layout is used with shield layer, then parasitic inductance is reduced, but board thickness dependency and design complexity increase
Solution Approach 1:
The patent transitions from a conventional lateral power loop layout to a vertical power loop layout that utilizes the third dimension (board thickness) by routing power and ground traces on opposite sides of the PCB and connecting them through vias. This dimensional change eliminates the need for shield layers while minimizing parasitic inductance through compact via placement directly beneath the power FETs.
Solution Approach 2:
The patent segments the power loop into distinct vertical components: power trace on top layer, ground trace on bottom layer, and connecting vias in between. This segmentation allows independent optimization of each component's position and size, enabling precise control over parasitic inductance without requiring additional shield layers.
2Productivity
If faster switching speeds are achieved with lower figure of merit devices, then converter efficiency improves, but voltage overshoot increases
Solution Approach 1:
The patent applies preliminary anti-action by pre-configuring the vertical power loop layout with optimally placed vias and minimized trace lengths before switching events occur. This pre-optimized low-inductance path counteracts the inherent voltage overshoot tendency of fast-switching devices by reducing the L di/dt effect, allowing fast switching speeds without excessive voltage overshoot.
3Loss of energy
If high frequency loop inductance is minimized, then efficiency improves, but layout complexity increases
Solution Approach 1:
The vertical power loop layout serves itself by using the necessary vias for component mounting and electrical connection as the primary means of achieving low inductance, rather than requiring separate optimization measures. The same vias that connect power and ground traces also define the current path, eliminating the need for additional shield layers or complex routing schemes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces parasitic inductance by 65% compared to conventional layouts, improves efficiency, and decreases voltage overshoot, while being independent of board thickness and eliminating the need for a shield layer, resulting in enhanced power converter performance.
Implementation Method 1
a first inner layer is utilized as a return path for the high frequency power loop current to minimize the physical size of the power loop and reduce parasitic inductance
Data Source
AI summary
A highly efficient, single sided circuit board layout design providing magnetic field self-cancellation and reduced parasitic inductance independent of board thickness. The low profile power loop extends through active and passive devices on the top layer of the circuit board, with vias connecting the power loop to a return path in an inner layer of the board. The magnetic effect of the portion of the power loop on the top layer is reduced by locating the inner layer return path directly underneath the power loop path on the top layer.