Multilayer PCB Via Structure for Soldering Heat Transfer
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Solution Overview
Problem
Poor solderability during the soldering of printed circuit boards leads to thermal stress and potential electrical connection failure due to heat transfer issues, which are exacerbated by increased through vias reducing wiring pattern freedom.
Innovation Solution
A printed circuit board design with alternating dielectric and conductive layers, through holes, through vias, and inner layer vias connected by conductive pattern layers, enhancing heat transfer paths while maintaining wiring flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If heat transfer paths are increased to improve solderability, then thermal efficiency is improved, but device complexity increases
Solution Approach 1:
The patent introduces inner layer vias that extend through multiple dielectric layers (from Mth to (N-1)th layer) to create additional vertical heat conduction paths within the multilayer structure. This dimensional approach allows heat to be conducted through more pathways without significantly increasing overall device footprint or complexity
Solution Approach 2:
The via structure is segmented into different types (through vias extending from first to (N-1)th layer, inner layer vias extending from Mth to (N-1)th layer) with conductors positioned at different locations. This segmentation allows optimized heat conduction paths while maintaining manufacturing feasibility and controlling structural complexity
2Temperature
If through vias are increased to improve heat transfer, then thermal efficiency is improved, but wiring pattern freedom is reduced
Solution Approach 1:
The patent applies different via configurations to different regions of the circuit board. Through vias are positioned at specific locations for heat conduction, while inner layer vias are strategically placed to maintain wiring flexibility in various regions. This localized approach ensures heat transfer optimization without uniformly constraining wiring patterns across the entire board
Solution Approach 2:
By utilizing vertical dimension with inner layer vias extending through multiple dielectric layers, the patent creates additional heat conduction pathways without consuming horizontal space that would be needed for wiring patterns. This dimensional separation allows both heat transfer optimization and wiring flexibility to coexist
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves thermal efficiency and ensures freedom in wiring pattern arrangement by increasing heat conduction paths without compromising design flexibility.
Implementation Method 1
heat generated during soldering is not easily transferred to a rear surface... heat transfer issues... improving thermal efficiency... increasing heat conduction paths
Data Source
AI summary
A printed circuit board includes a plurality of dielectric layers, a plurality of conductive pattern layers alternately laminated with the plurality of dielectric layers, a through hole penetrating through the plurality of the dielectric layers, a through via penetrating through the plurality of dielectric layers, and an inner layer via. The inner layer via penetrates through each dielectric layer from an Mth dielectric layer to the (N-1)th dielectric layer, where M is an integer that is greater than or equal to two and less than or equal to (N−1), and has an inner circumferential surface on which an inner layer via conductor is disposed. The through via and the inner layer via are connected to each other with at least one conductive pattern layer that is selected from a second conductive pattern layer to an (N-1)th conductive pattern layer in the plurality of conductive pattern layers.