Multilayer Pixel Circuit Layout for High-Resolution Displays

The patent transitions from a conventional single-layer planar arrangement to a multi-layer three-dimensional stacked configuration. Transistors are distributed across multiple semiconductor layers (first, second, and third semiconductor layers) with channel areas positioned at different heights, while capacitors are stacked vertically between these layers. This dimensional transition enables higher integration density and resolution by utilizing the vertical space rather than being constrained to a two-dimensional plane.

The patent implements a nested structure where capacitors are positioned between and around transistor components in a hierarchical arrangement. Specifically, first capacitors are located between the first and second semiconductor layers, second capacitors between the second and third layers, and third capacitors within the third semiconductor layer structure. This nesting approach maximizes space utilization and achieves high integration density without requiring excessive lateral area.

The patent resolves connection complexity by transitioning to a multi-layer vertical architecture. Instead of requiring extensive lateral interconnections in a single plane, the invention uses vertical stacking to position components closer together in the third dimension. The channel areas of transistors in different layers are aligned vertically, and capacitors are positioned between layers, reducing the lateral distance for electrical connections and simplifying the interconnect structure despite increased component density.

The patent merges multiple transistor and capacitor components into a tightly integrated multi-layer assembly. The first, second, and third transistors with their respective channel areas are combined in a stacked configuration, along with multiple capacitor structures positioned between and within the layers. This merging approach creates a compact pixel circuit unit that achieves high integration while sharing common structural elements and interconnection paths across the layers.

The patent segments the transistor components into distinct semiconductor layers, with each layer containing specific transistor elements (first transistor in the first layer, second transistor in the second layer, third transistor in the third layer). This segmentation allows for modular fabrication where each layer can be processed and formed separately through sequential deposition and patterning steps, making the multi-layer structure more manageable despite the increased manufacturing complexity.

The patent employs preliminary formation of lower layers before constructing upper layers. The first semiconductor layer with its transistor and capacitor structures is formed first, followed by the second semiconductor layer stacked above it, and finally the third semiconductor layer. This sequential preliminary action approach allows each layer to be optimized and processed independently, with subsequent layers built upon the established structure below, facilitating a systematic multi-layer fabrication process.