Multi-Layer Pixel Circuit Structure for Higher Display Resolution
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Solution Overview
Problem
Existing display devices face challenges in efficiently arranging and connecting thin film transistors, capacitors, and lines to achieve high-resolution displays with improved image quality and efficient space utilization.
Innovation Solution
A display device with a multi-layer structure of transistors and capacitors stacked in one direction, where each transistor has a distinct channel area in a different semiconductor layer, and capacitors are implemented as a multi-capacitor structure, enhancing integration and resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If transistors and capacitors are arranged in a conventional planar structure, then the device complexity is lower and manufacturing is easier, but the area occupied by pixel circuits increases and resolution decreases
Solution Approach 1:
The patent transitions from a conventional planar (2D) arrangement of transistors and capacitors to a three-dimensional stacked structure where multiple transistor layers (first through fourth transistors in different semiconductor layers) and capacitor layers are vertically integrated. This dimensional change allows pixel circuits to be compacted significantly, reducing the horizontal area occupied while maintaining full functionality, thereby enabling higher display resolution without sacrificing manufacturing feasibility.
Solution Approach 2:
The patent implements a nested structure where multiple transistor layers and capacitor layers are stacked vertically, with each layer containing complete transistor structures (source, drain, channel areas) that are interconnected through vertical connections. The first through fourth transistors are nested in different semiconductor layers, with capacitors nested between these layers, creating a compact vertical integration that reduces overall pixel circuit footprint while maintaining electrical functionality.
2Manufacturing precision
If multiple transistor layers are stacked vertically, then the degree of integration increases and resolution improves, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the pixel circuit into multiple discrete transistor layers (first through fourth transistors in separate semiconductor layers), with each layer containing specific transistor structures that perform distinct functions. This segmentation allows for modular manufacturing where each layer can be processed and integrated separately, reducing the overall complexity of creating a fully functional multi-layer pixel circuit while achieving high integration density.
Solution Approach 2:
The patent employs multiple capacitor layers (first, second, and third capacitors in different conductive layers) that serve both as storage elements and as interlayer connection structures. These capacitors are positioned to overlap with transistor regions in adjacent layers, enabling them to function simultaneously as electrical storage devices and as structural bridges that simplify the interconnection architecture, thereby reducing overall device complexity despite the multi-layer configuration.
Data Source
AI summary
A display device includes a light-emitting element, a first transistor that generates a driving current applied to the light-emitting element and includes a first channel area, a second transistor that applies a data voltage to the first transistor in response to a first gate signal and includes a second channel area disposed in a different layer from the first channel area, a third transistor that applies a power voltage to the first transistor in response to a second gate signal and includes a third channel area disposed in a different layer from each of the first channel area and the second channel area, and a fourth transistor that electrically connects the first transistor and the light-emitting element in response to a light-emitting signal and includes a fourth channel area disposed in a different layer from each of the first channel area and the second channel area.