Display Panel Multilayer Routing for Dense Pixel Circuits
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Solution Overview
Problem
The challenge of arranging electronic elements of various configurations in a narrow area to manufacture high-resolution display devices has increased with the diversification of display device uses.
Innovation Solution
A display panel design with specific configurations of pixel circuits, including driving transistors, capacitors, and light-emitting diodes, utilizing horizontal and vertical voltage lines, gate lines, and a bottom metal layer to optimize element arrangement and improve resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If electronic elements are arranged in a narrow area to achieve high resolution, then display resolution is improved, but device complexity increases
Solution Approach 1:
The patent employs multi-layer stacking of conductive lines (first horizontal voltage line, second horizontal voltage line at different layers, gate lines, vertical voltage lines) to route signals in three-dimensional space rather than two dimensions. This vertical dimensionality allows numerous electronic elements to be interconnected in a compact area without excessive planar complexity, enabling high-resolution pixel arrangements while managing routing complexity through layered architecture.
Solution Approach 2:
The conductive routing is segmented into multiple specialized lines: first horizontal voltage lines for anode connections, second horizontal voltage lines for cathode connections, gate lines for transistor control, and vertical voltage lines for inter-row communication. This segmentation of routing functions allows each line type to be optimized independently, reducing overall system complexity while achieving high-resolution pixel density through systematic organization.
2Area of stationary object
If multiple conductive lines are arranged closely to improve pixel density, then area utilization is improved, but signal interference increases
Solution Approach 1:
By routing different signal types (horizontal voltage lines, gate lines, vertical voltage lines) through different vertical layers rather than crowding them in the same plane, the patent reduces capacitive coupling and electromagnetic interference between adjacent lines. The multi-layer architecture maintains high pixel density by utilizing the third dimension for signal separation, thereby minimizing interference while maximizing area utilization.
Solution Approach 2:
Insulating layers are introduced as intermediary materials between adjacent conductive lines at different layers. These insulating layers act as mediators that electrically isolate signal-carrying lines, preventing direct interference while allowing the lines to be positioned in close proximity for high-density routing. This enables compact pixel circuits without sacrificing signal integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances display quality by ensuring accurate black luminance and contrast ratio, reducing power consumption, and maintaining color consistency, suitable for high-resolution displays.
Implementation Method 1
a first light-emitting diode electrically connected to the first pixel circuit; a second light-emitting diode electrically connected to the second pixel circuit
Data Source
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AI summary
A display panel includes: first and second pixel circuits adjacent to each other in a first direction; a first light-emitting diode, LED, electrically connected to the first pixel circuit; a second LED electrically connected to the second pixel circuit; a first horizontal voltage line extending in the first direction, and electrically connected to a semiconductor layer of a first transistor; a second horizontal voltage line extending in the first direction, and electrically connected to a semiconductor layer of a second transistor; and a first gate line extending in the first direction, and electrically connected to each of a gate electrode of the first transistor of the first pixel circuit and a gate electrode of the second transistor of the second pixel circuit. The first horizontal voltage line and the second horizontal voltage line are at different layers from each other, and overlap with each other in a plan view.